TECHNIQUES FOR APPROXIMATING A DIFFERENCE BETWEEN TWO CAPACITANCES

• US 20120024064A1
• Filed: 07/29/2010
• Published: 02/02/2012
• Est. Priority Date: 07/29/2010
• Status: Active Grant

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Tyler, Larry E., Wu, Jin Yong
• Granted Patent: US 8,688,393 B2
• Time in Patent Office: Days
• US Class Current: 73/514.32
• CPC Class Codes: A61N 1/36542 controlled by body motion, e.g. acceleration
• CPC Class Codes: A61N 1/36578 controlled by mechanical motion of the heart wall, e.g. measured by an accelerometer or microphone
• CPC Class Codes: G01D 5/24 by varying capacitance
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24

Abstract

A system includes a capacitance adjustment module and a control module. The capacitance adjustment module is configured to connect one or more of N capacitors in parallel with one of a first and second capacitance. The control module identifies the smaller of the first and second capacitances and identifies the larger of the first and second capacitances. Subsequently, the control module, during each of M iterations, instructs the capacitance adjustment module to connect at least one of the N capacitors across a set of nodes in parallel with the smaller identified capacitance, and determines whether the capacitance associated with the set of nodes is greater than the larger identified capacitance. After the M iterations, the control module approximates the difference between the first and second capacitances based on which of the N capacitors are connected across the nodes. M and N are integers greater than or equal to 1.

Claims

1. A system comprising:

a capacitance adjustment module configured to connect one or more of N capacitors in parallel with one of a first and second capacitance; and

a control module that identifies the smaller of the first and second capacitances, that identifies the larger of the first and second capacitances, and that subsequently, during each of M iterations;

instructs the capacitance adjustment module to connect at least one of the N capacitors across a set of nodes in parallel with the smaller identified capacitance; and

determines whether the capacitance associated with the set of nodes is greater than the larger identified capacitance,

wherein, after the M iterations, the control module approximates the difference between the first and second capacitances based on which of the N capacitors are connected across the set of nodes, where M and N are integers greater than or equal to 1.

2. The system of claim 1, wherein the control module instructs the capacitance adjustment module to connect a different combination of the N capacitors during each of the M iterations.

3. The system of claim 1, wherein the control module, during each of the M iterations, instructs the capacitance adjustment module to disconnect the at least one of the N capacitors when the capacitance associated with the set of nodes is greater than the larger identified capacitance.

4. The system of claim 1, wherein the N capacitors have binary-weighted values.

5. The system of claim 1, further comprising a capacitance comparison module that delivers current to the first and second capacitances and that determines which of the first and second capacitances is smaller.

6. The system of claim 5, wherein the capacitance comparison module determines which of the first and second capacitances is smaller based on which of the first and second capacitances develops voltage at a higher rate in response to the current.

7. The system of claim 6, wherein the control module identifies the smaller and larger of the first and second capacitances based on which of the first and second capacitances develops voltage at a higher rate.

8. The system of claim 1, wherein the control module instructs the capacitance adjustment module using a binary value that indicates which of the one or more of the N capacitors to connect.

9. The system of claim 8, wherein each bit of the binary value corresponds to one of the N capacitors.

10. The system of claim 1, wherein the control module instructs the capacitance adjustment module using a binary value that indicates which of the one or more of the N capacitors to disconnect.

11. The system of claim 1, wherein the control module instructs the capacitance adjustment module to connect the one of the N capacitors across the set of nodes using a binary value that indicates the set of nodes.

12. The system of claim 1, further comprising a capacitance comparison module that delivers current to the larger identified capacitance and the capacitance associated with the set of nodes, and that determines when the capacitance associated with the set of nodes is greater than the larger identified capacitance based on which of the larger identified capacitance and the capacitance associated with the set of nodes develops voltage at a higher rate.

13. The system of claim 12, wherein the control module determines whether the capacitance associated with the set of nodes is greater than the larger identified capacitance based on which of the larger identified capacitance and the capacitance associated with the set of nodes develops voltage at a higher rate.

14. The system of claim 1, wherein N is equal to M.

15. The system of claim 1, wherein the first and second capacitances are included in an accelerometer, and wherein the control module determines an approximate acceleration of the accelerometer based on the approximated difference between the first and second capacitances.

16. The system of claim 15, further comprising a zeroing capacitance module configured to add capacitors to one of the first and second capacitances, wherein the control module instructs the zeroing capacitance module to add capacitors to one of the first and second capacitances such that a difference between the first and second capacitances is decreased when the accelerometer is not subject to acceleration.

17. The system of claim 1, further comprising a capacitance compensation module configured to add capacitors to the larger identified capacitance such that the added capacitors are equal to parasitic capacitances associated with the capacitors connected in parallel with the smaller identified capacitance.

18. The system of claim 1, wherein, after the M iterations, the control module determines that the approximate difference between the first and second capacitances is equal to the sum of the capacitors connected across the set of nodes.

19. A method comprising:

identifying the smaller of a first capacitance and a second capacitance;

identifying the larger of the first and second capacitances;

during each of M iterations;

connecting at least one of N capacitors across a set of nodes in parallel with the smaller identified capacitance; and

determining whether the capacitance associated with the set of nodes is greater than the larger identified capacitance; and

after the M iterations, approximating the difference between the first and second capacitances based on which of the N capacitors are connected across the set of nodes, where M and N are integers greater than or equal to 1.

20. The method of claim 19, further comprising connecting a different combination of the N capacitors during each of the M iterations.

21. The method of claim 19, further comprising, during each of the M iterations, disconnecting the at least one of the N capacitors when the capacitance associated with the set of nodes is greater than the larger identified capacitance.

22. The method of claim 19, wherein the N capacitors have binary-weighted values.

23. The method of claim 19, wherein N is equal to M.

24. The method of claim 19, further comprising, after the M iterations, determining that the approximate difference between the first and second capacitances is equal to the sum of the capacitors connected across the set of nodes.

25. The method of claim 19, further comprising:

delivering current to the first and second capacitances; and

determining which of the first and second capacitances is smaller based on which of the first and second capacitances develops voltage at a higher rate in response to the current.

26. The method of claim 19, further comprising one of connecting or disconnecting the at least one of the N capacitors using a binary value that indicates which of the N capacitors to connect or disconnect, wherein each bit of the binary value corresponds to one of the N capacitors.

27. The method of claim 19, further comprising connecting the one of the N capacitors across the set of nodes using a binary value that indicates the set of nodes.

28. A system comprising:

means for identifying the smaller of a first capacitance and a second capacitance;

means for identifying the larger of the first and second capacitances;

means for, during each of M iterations;

connecting at least one of N capacitors across a set of nodes in parallel with the smaller identified capacitance; and

determining whether the capacitance associated with the set of nodes is greater than the larger identified capacitance; and

means for, after the M iterations, approximating the difference between the first and second capacitances based on which of the N capacitors are connected across the set of nodes, where M and N are integers greater than or equal to 1.

29. The system of claim 28, further comprising means for connecting a different combination of the N capacitors during each of the M iterations.

30. The system of claim 28, further comprising means for, during each of the M iterations, disconnecting the at least one of the N capacitors when the capacitance associated with the set of nodes is greater than the larger identified capacitance.

31. The system of claim 28, wherein the N capacitors have binary-weighted values.

32. The system of claim 28, wherein N is equal to M.

33. The system of claim 28, further comprising, after the M iterations, means for determining that the approximate difference between the first and second capacitances is equal to the sum of the capacitors connected across the set of nodes.

34. The system of claim 28, further comprising:

means for delivering current to the first and second capacitances; and

means for determining which of the first and second capacitances is smaller based on which of the first and second capacitances develops voltage at a higher rate in response to the current.

35. The system of claim 28, further comprising means for one of connecting or disconnecting the at least one of the N capacitors using a binary value that indicates which of the N capacitors to connect or disconnect, wherein each bit of the binary value corresponds to one of the N capacitors.

36. A system comprising:

a capacitance adjustment module configured to connect one or more of N capacitors in parallel with a first capacitance and configured to connect an offset capacitor having a predetermined value in parallel with a second capacitance; and

a control module that, during each of M iterations;

instructs the capacitance adjustment module to connect at least one of the N capacitors across a set of nodes in parallel with the first capacitance; and

determines whether the capacitance associated with the set of nodes is greater than the offset capacitor in parallel with the second capacitance,

wherein, after the M iterations, the control module approximates the difference between the first and second capacitances based on which of the N capacitors are connected across the set of nodes, where M and N are integers greater than or equal to 1.

37. The system of claim 36, wherein the control module instructs the capacitance adjustment module to connect a different combination of the N capacitors during each of the M iterations.

38. The system of claim 36, wherein the control module, during each of the M iterations, instructs the capacitance adjustment module to disconnect the at least one of the N capacitors when the capacitance associated with the set of nodes is greater than the offset capacitor in parallel with the second capacitance.

39. The system of claim 36, wherein the N capacitors include at least one capacitor having a value that is equal to the value of the offset capacitor.

40. The system of claim 36, wherein the value of the offset capacitor is selected such that the value of the offset capacitor is greater than or equal to a maximum difference between the first and second capacitances.

41. The system of claim 36, wherein the first and second capacitances are included in a sensor, and wherein the control module approximates a parameter measured by the sensor based on the difference between the first and second capacitances.

42. A system comprising:

a capacitance adjustment module configured to connect one or more of N capacitors across a set of nodes;

a capacitance comparison module configured to;

connect to the set of nodes;

connect to a target capacitance; and

determine which of the target capacitance and a capacitance associated with the set of nodes is larger; and

a control module that, during each of M iterations;

instructs the capacitance adjustment module to connect at least one of the N capacitors across the set of nodes; and

instructs the capacitance comparison module to determine which of the target capacitance and the capacitance associated with the set of nodes is larger,

wherein, after the M iterations, the control module approximates the target capacitance based on which of the N capacitors are connected across the set of nodes, where M and N are integers greater than or equal to 1.

43. The system of claim 42, wherein the control module instructs the capacitance adjustment module to connect a different combination of the N capacitors during each of the M iterations.

44. The system of claim 42, wherein the control module, during each of the M iterations, instructs the capacitance adjustment module to disconnect the at least one of the N capacitors when the capacitance associated with the set of nodes is larger than the target capacitance.