NANOSTRUCTURE ARRAY TRANSISTOR

• US 20120025169A1
• Filed: 08/02/2010
• Published: 02/02/2012
• Est. Priority Date: 08/02/2010
• Status: Abandoned Application

• Current Assignee: Sundiode, Inc.
• Original Assignee: Sundiode, Inc.
• Inventors: Mars, Danny E., Kim, James C., Yi, Sungsoo
• Application Number:
  US12/848,722
• Publication Number:
  US 20120025169A1
• Time in Patent Office: Days
• US Class Current: 257/24
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/6631 with an active layer made of a group 13/15 material
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/66856 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7788 Vertical transistors
• CPC Class Codes: H01L 29/7789 the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
• CPC Class Codes: H01L 29/8122 Vertical transistors SIT, PBT H01L29/7722

Abstract

Transistors and methods for forming transistors from groups of nanostructures are disclosed herein. The transistor may be formed from an array of nanostructures that are grown vertically on a substrate. The nanostructures may have lower, middle and upper segments that may be formed with different materials and/or doping to achieve desired effects. Collectively, the lower segments may form the source or drain, with the middle segments collectively forming the channel. Alternatively, the lower segments could collectively form the emitter or collector, with the middle segments collectively forming the base. Transistor electrodes may be planar metal structures that surround sidewalls of the nanostructures. The transistors may be Field Effect Transistors (FETs) or bipolar junction transistors (BJTs). Heterojunction bipolar junction transistors (HBTs) and high electron mobility transistors (HEMTs) are possible.

Claims

1. A transistor comprising:

an array of nanostructures, wherein nanostructures in the array of nanostructures include first segments, second segments, and third segments, the second segments are between the first and third segments;

a first electrode in electrical contact with the first segments of the nanostructures;

a second electrode surrounding ones of the second segments of the nanostructures; and

a third electrode in electrical contact with the third segments of the nanostructures.

2. The transistor of claim 1, wherein the transistor is a field effect transistor.

3. The transistor of claim 1, wherein the transistor is a bipolar junction transistor.

4. The transistor of claim 1, wherein the first segments and the third segments are doped with a material having a first type of conductivity.

5. The transistor of claim 4, wherein the second segments are doped with a material having a second type of conductivity that is opposite the first type of conductivity.

6. The transistor of claim 4, wherein the second segments are not intentionally doped.

7. The transistor of claim 1, wherein the array of nanostructures is aligned perpendicular with respect to the surface of a substrate.

8. The transistor of claim 1, wherein the first, the second, and the third electrodes have a planar structure that is aligned horizontally with respect to the surface of a substrate.

9. The transistor of claim 1, wherein the third electrode surrounds sidewalls of ones of the nanostructures.

10. The transistor of claim 9, wherein the first electrode surrounds sidewalls of ones of the nanostructures.

11. The transistor of claim 1, wherein the first segments are either a drain or a source of the transistor, the second segments form a channel of the transistor, and the third segments are either a source or a drain of the transistor.

12. The transistor of claim 1, wherein the first segments are either an emitter or a collector of the transistor, the second segments form a base of the transistor, and the third segments are either a collector or an emitter of the transistor.

13. The transistor of claim 1, wherein the second electrode forms a Schottky contact with the second segments of the nanostructures.

14. The transistor of claim 1, wherein the first, the second and the third electrodes form an Ohmic contact with the array of nano structures.

15. The transistor of claim 1, wherein the first, the second and the third electrodes include metal.

16. The transistor of claim 1, wherein the nanostructures include a nitride semiconductor.

17. The transistor of claim 1, further comprising a high bandgap region at least partially around ones of the second segments, the high bandgap region is between the second electrode and the second segments, the high bandgap region includes a first material having a first bandgap, the second segments include a second material having a second bandgap, the first bandgap is greater than the second bandgap.

18. A method of forming a transistor comprising:

forming an array of nanostructures, including forming first segments, second segments, and third segments in the nanostructures, the second segments are between the first and the third segments;

forming a first electrode in electrical contact with the first segments of the nanostructures;

forming a second electrode surrounding ones of the second segments of the nanostructures; and

forming a third electrode in electrical contact with the third segments of the nanostructures.

19. The method of claim 18, wherein forming an array of nanostructures includes growing the nanostructures vertically on a substrate.

20. The method of claim 18, wherein the forming the first, the second, and the third electrodes includes forming planar structures that are horizontal to a substrate.

21. The method of claim 18, wherein forming the first, the second, and the third electrodes includes:

forming a first layer of metal around sidewalls of the nanostructures,

forming a second layer of metal around the sidewalls of the nanostructures; and

forming a third layer of metal around the sidewalls of the nanostructures.

22. The method of claim 21, further comprising:

forming a first layer of insulation over the first layer of metal and around the sidewalls of the nano structures; and

forming a second layer of insulation over the second layer of metal and around the sidewalls of the nanostructures.

23. The method of claim 18, wherein the forming an array of nanostructures includes doping the first segments and the third segments with a material having a first type of conductivity.

24. The method of claim 23, wherein the forming an array of nanostructures includes doping the second segments with a material having a second type of conductivity that is opposite the first type.

25. The method of claim 18, wherein the forming an array of nanostructures includes not intentionally doping the second segments.

26. The method of claim 18, wherein forming the second electrode includes forming a Schottky contact with the second segments.

27. The method of claim 18, further comprising forming a high bandgap region at least partially around the ones of the second segments, wherein the second electrode is formed around the high bandgap region, wherein the high bandgap region is formed from a first material having a first bandgap, wherein the second segments are formed from a second material having a second bandgap, the first bandgap is greater than the second bandgap.

28. A field effect transistor comprising:

an array of nanostructures, the nanostructures having lower segments, middle segments, and upper segments, the upper segments and the lower segments are doped with a material having a first type of conductivity;

a first source/drain electrode in electrical contact with the lower segments of the array of nano structures;

a gate electrode surrounding ones of the middle segments of the plurality of nanostructures; and

a second source/drain electrode in electrical contact with the upper segments.

29. The field effect transistor of claim 28, wherein:

the middle segments are not intentionally doped.

30. The field effect transistor of claim 28, further comprising a high bandgap region between ones of the second segments and the gate electrode, the high bandgap region includes a first material having a first bandgap, the second segments include a second material having a second bandgap, the first bandgap is greater than the second bandgap.

31. The field effect transistor of claim 28, wherein the second source/drain electrode surrounds ones of the upper segments of the plurality of nanostructures.

32. The field effect transistor of claim 31, wherein the first source/drain electrode surrounds ones of the lower segments of the plurality of nanostructures.

33. The field effect transistor of claim 28, wherein the gate electrode forms a Schottky contact with the middle segments.

34. A bipolar junction transistor comprising:

an array of nanostructures, the nanostructures having lower segments, middle segments, and upper segments, the upper segments and the lower segments are doped with a material having a first type of conductivity, the middle segments are doped with a material having a second type of conductivity;

a first emitter/collector electrode in electrical contact with the lower segments of the array of nanostructures;

a base electrode in electrical contact with the middle segments of the plurality of nanostructures; and

a second emitter/collector electrode in electrical contact with the upper segments.

35. The bipolar junction transistor of claim 34, wherein the transistor is a heterojunction bipolar junction transistor.

36. The bipolar junction transistor of claim 34, wherein the base electrode surrounds ones of the middle segments, wherein the second emitter/collector electrode surrounds ones of the upper segments.

37. The bipolar junction transistor of claim 36, wherein the first emitter/collector electrode surrounds ones of the lower segments.