Transistors, methods of manufacturing transistors, and electronic devices including transistors

• US 20120025187A1
• Filed: 03/24/2011
• Published: 02/02/2012
• Est. Priority Date: 07/30/2010
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Kyung-bae, Ryu, Myung-kwan, Lee, Sang-yoon, Lee, Kwang-hee, Kim, Tae-sang, Kim, Eok-su, Son, Kyoung-seok, Kim, Hyun-suk, Maeng, Wan-joo, Park, Joon-seok
• Application Number:
  US13/064,428
• Publication Number:
  US 20120025187A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Transistors, methods of manufacturing the transistors, and electronic devices including the transistors. The transistor may include an oxide channel layer having a multi-layer structure. The channel layer may include a first layer and a second layer that are sequentially arranged from a gate insulation layer. The first layer may be a conductor, and the second layer may be a semiconductor having a lower electrical conductivity than that of the first layer. The first layer may become a depletion region according to a gate voltage condition.

Claims

1. A transistor comprising:

a channel layer including first and second layers, the first layer configured to switch between a normally conductive state and a depletion state according to a voltage bias, a conductivity of the second layer less than a conductivity of the first layer in the conductive state, the channel layer including an oxide;

a source and a drain on the channel layer;

a gate on the channel layer; and

a gate insulation layer between the first layer and the gate, the first layer between the second layer and the gate insulation layer.

2. The transistor of claim 1, wherein an oxygen vacancy concentration of the first layer is higher than an oxygen vacancy concentration of the second layer.

3. The transistor of claim 1, wherein the conductivity of the first layer is greater than or equal to about 10³ S/cm in the normally conductive state.

4. The transistor of claim 1, wherein the conductivity of the second layer is greater than or equal to about 10⁻

8 S/cm and less than about 10³ S/cm.

5. The transistor of claim 1, wherein a carrier concentration of the first layer is greater than or equal to about 10¹⁸/cm³ and less than or equal to about 10²¹/cm³.

6. The transistor of claim 1, wherein a carrier concentration of the second layer is greater than or equal to about 10¹³/cm³ and less than about 10¹⁸/cm³.

7. The transistor of claim 1, wherein a thickness of the first layer is about 5 nm to about 50 nm.

8. The transistor of claim 1, wherein the first layer and the second layer include a same metal composition.

9. The transistor of claim 1, wherein a metal concentration of the first layer is the same as a metal concentration of the second layer.

10. The transistor of claim 1, wherein the oxide of the channel layer is at least one of a ZnO-based oxide and an InO-based oxide.

11. The transistor of claim 1, wherein the gate is a bottom gate.

12. The transistor of claim 11, further comprising:

an etch stop layer on the channel layer.

13. The transistor of claim 1, wherein the gate is a top gate.

14. The transistor of claim 1, wherein the first layer is insulative in the depletion state.

15. A flat panel display comprising the transistor of claim 1.

16. A method of manufacturing a transistor, the method comprising:

forming a gate;

forming a channel layer including an oxide by sequentially forming first and second layers corresponding to the gate, the first layer formed to be switchable between a conductive state and a depletion state according to a voltage bias, the second layer formed with a conductivity that is less than a conductivity of the first layer in the conductive state;

forming a gate insulation layer between the gate and the first layer; and

forming a source and drain on the channel layer.

17. The method of claim 16, wherein the forming of the channel layer includes forming the first layer at a first oxygen partial pressure, and forming the second layer at a second oxygen partial pressure that is greater than the first oxygen partial pressure.

18. The method of claim 17, wherein the forming of the channel layer includes using a reaction gas including O₂ and Ar,

forming the first layer at an O₂ to Ar (O₂/Ar) flow rate of greater than 0 and less than about 0.1, and

forming the second layer at an O₂ to Ar (O₂/Ar) flow rate of greater than or equal to about 0.1.

19. The method of claim 16, wherein the forming of the channel layer includes forming the first and second layers using an in-situ process.

20. The method of claim 19, wherein the forming of the first and second layers using the in-situ process includes only varying one or more of oxygen partial pressure, chamber pressure and source power.

21. The method of claim 16, wherein the forming of the channel layer includes forming the first layer with an oxygen vacancy concentration that is higher than an oxygen vacancy concentration of the second layer.

22. The method of claim 16, wherein the forming of the channel layer includes forming the first layer so that the conductivity of the first layer is greater than or equal to about 10³ S/cm.

23. The method of claim 16, wherein the forming of the channel layer includes forming the second layer so that the conductivity of the second layer is greater than or equal to about 10⁻

8 S/cm and less than about 10³ S/cm.

24. The method of claim 16, wherein the forming of the channel layer includes forming the first layer to a thickness of about 5 nm to about 50 nm.

25. The method of claim 16, wherein the channel layer includes at least one of a ZnO-based oxide and an InO-based oxide.

26. The method of claim 16, wherein the forming of the gate includes forming the gate to be at least one of a bottom gate and a top gate.