Semiconductor Device and Manufacturing Method Thereof

• US 20120025191A1
• Filed: 07/27/2011
• Published: 02/02/2012
• Est. Priority Date: 07/30/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Granted Patent: US 9,559,211 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/30612 Etching of AIIIBV compounds
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A method for manufacturing a semiconductor device, which enables miniaturization and reduction of defect, is provided. It includes forming an oxide semiconductor layer, and source and drain electrodes in contact with the oxide semiconductor layer, over an insulating surface; forming insulating layers over the source electrode and the drain electrode; forming a gate insulating layer over the oxide semiconductor layer, the source and drain electrodes, and the insulating layer; forming a conductive layer over the gate insulating layer; forming an insulating film covering the conductive layer; processing the insulating film so that at least part of a region of the conductive layer, which overlaps with the source electrode or the drain electrode, is exposed; and etching the exposed region of the conductive layer to form a gate electrode overlapping with at least part of the region sandwiched between the source electrode and the drain electrode, in a self-aligned manner.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer on an insulating surface;

forming a source electrode in contact with the oxide semiconductor layer;

forming a drain electrode in contact with the oxide semiconductor layer;

forming a first insulating layer over the source electrode;

forming a second insulating layer over the drain electrode;

forming a gate insulating layer over the oxide semiconductor layer, the source electrode, the drain electrode, the first insulating layer, and the second insulating layer;

forming a conductive layer over the gate insulating layer so that the conductive layer overlaps with at least a part of a region sandwiched between the source electrode and the drain electrode;

forming an insulating film so that the insulating film covers the conductive layer;

processing the insulating film so that at least parts of regions of the conductive layer, which overlap with the source electrode and the drain electrode, are exposed; and

etching the exposed regions of the conductive layer, thereby forming a gate electrode overlapping with at least the part of the region sandwiched between the source electrode and the drain electrode in a self-aligned manner.

2. The method for manufacturing a semiconductor device, according to claim 1,

wherein each of the source electrode and the drain electrode is formed to have a tapered portion,

wherein the gate electrode is formed to have a inverse tapered portion below an uppermost surface of the gate insulating layer, and

wherein only a part of the inverse tapered portion of the gate electrode below the uppermost surface of the gate insulating layer overlaps with a part of the tapered portion of one of the source electrode and the drain electrode.

3. The method for manufacturing a semiconductor device, according to claim 2,

wherein the gate electrode is formed to have a tapered portion over the uppermost surface of the gate insulating layer, and

wherein only a part of the tapered portion of the gate electrode over the uppermost surface of the gate insulating layer overlaps with the part of the tapered portion of one of the source electrode and the drain electrode.

4. The method for manufacturing a semiconductor device, according to claim 1, wherein the gate electrode does not overlap with the source electrode and the drain electrode.

5. The method for manufacturing a semiconductor device, according to claim 1,

wherein the source electrode is in contact with at least a part of a top surface of the oxide semiconductor layer, and

wherein the drain electrode is in contact with at least a part of the top surface of the oxide semiconductor layer.

6. The method for manufacturing a semiconductor device, according to claim 1, wherein the oxide semiconductor layer is in contact with at least a part of a top surface of the source electrode and at least a part of a top surface of the drain electrode.

7. The method for manufacturing a semiconductor device, according to claim 1, wherein a part of the conductive layer, which is left in the etching step, is processed to form a wiring.

8. The method for manufacturing a semiconductor device, according to claim 1, wherein a distance between edges of the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 200 nm.

9. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer on an insulating surface;

forming a source electrode in contact with the oxide semiconductor layer;

forming a drain electrode in contact with the oxide semiconductor layer;

forming a first insulating layer over the source electrode;

forming a second insulating layer over the drain electrode;

forming a gate insulating layer over the oxide semiconductor layer, the source electrode, the drain electrode, the first insulating layer, and the second insulating layer;

forming a conductive layer over the gate insulating layer so that the conductive layer overlaps with at least a part of a region sandwiched between the source electrode and the drain electrode;

processing the conductive layer so that at least parts of regions of the gate insulating layer, which overlap with the source electrode and the drain electrode, are exposed, thereby forming a gate electrode overlapping with at least the part of the region sandwiched between the source electrode and the drain electrode in a self-aligned manner.

10. The method for manufacturing a semiconductor device, according to claim 9,

wherein each of the source electrode and the drain electrode is formed to have a tapered portion,

wherein the gate electrode is formed to have a inverse tapered portion below an uppermost surface of the gate insulating layer, and

wherein only a part of the inverse tapered portion of the gate electrode below the uppermost surface of the gate insulating layer overlaps with a part of the tapered portion of one of the source electrode and the drain electrode.

11. The method for manufacturing a semiconductor device, according to claim 9, wherein the gate electrode does not overlap with the source electrode and the drain electrode.

12. The method for manufacturing a semiconductor device, according to claim 9, wherein a top surface of the gate electrode is at a level lower than a level of an uppermost surface of the gate insulating layer.

13. The method for manufacturing a semiconductor device, according to claim 9,

wherein the source electrode is in contact with at least a part of a top surface of the oxide semiconductor layer, and

wherein the drain electrode is in contact with at least a part of the top surface of the oxide semiconductor layer.

14. The method for manufacturing a semiconductor device, according to claim 9, wherein the oxide semiconductor layer is in contact with at least a part of a top surface of the source electrode and at least a part of a top surface of the drain electrode.

15. The method for manufacturing a semiconductor device, according to claim 9, wherein a part of the conductive layer, which is left in the etching step, is processed to form a wiring.

16. The method for manufacturing a semiconductor device, according to claim 9, wherein a distance between edges of the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 200 nm.

17. A semiconductor device comprising:

an oxide semiconductor layer on an insulating surface;

a source electrode in contact with the oxide semiconductor layer;

a drain electrode in contact with the oxide semiconductor layer;

a first insulating layer over the source electrode;

a second insulating layer over the drain electrode;

a gate insulating layer over the oxide semiconductor layer, the source electrode, the drain electrode, the first insulating layer, and the second insulating layer; and

a gate electrode that is formed in a self-aligned manner to overlap with at least a part of a region sandwiched between the source electrode and the drain electrode.

18. The semiconductor device, according to claim 17, wherein a top surface of the gate electrode is at a level higher than a level of an uppermost surface of the gate insulating layer.

19. The semiconductor device, according to claim 17, wherein a top surface of the gate electrode is at a level lower than a level of an uppermost surface of the gate insulating layer.

20. The semiconductor device, according to claim 17,

wherein each of the source electrode and the drain electrode is formed to have a tapered portion,

wherein the gate electrode is formed to have a inverse tapered portion below an uppermost surface of the gate insulating layer, and

wherein only a part of the inverse tapered portion of the gate electrode below the uppermost surface of the gate insulating layer overlaps with a part of the tapered portion of one of the source electrode and the drain electrode.

21. The semiconductor device, according to claim 18,

wherein each of the source electrode and the drain electrode is formed to have a tapered portion,

wherein the gate electrode is formed to have a tapered portion below the uppermost surface of the gate insulating layer,

wherein only a part of the tapered portion of the gate electrode below the uppermost surface of the gate insulating layer overlaps with a part of the tapered portion of one of the source electrode and the drain electrode,

wherein the gate electrode is formed to have a tapered portion over the uppermost surface of the gate insulating layer, and

wherein only a part of the tapered portion of the gate electrode over the uppermost surface of the gate insulating layer overlaps with the part of the tapered portion of one of the source electrode and the drain electrode.

22. The semiconductor device, according to claim 17, wherein the gate electrode does not overlap with the source electrode and the drain electrode.

23. The semiconductor device, according to claim 17,

wherein the source electrode is in contact with at least a part of a top surface of the oxide semiconductor layer, and

wherein the drain electrode is in contact with at least a part of the top surface of the oxide semiconductor layer.

24. The semiconductor device, according to claim 17, wherein the oxide semiconductor layer is in contact with at least a part of a top surface of the source electrode and at least a part of a top surface of the drain electrode.

25. The semiconductor device, according to claim 17, wherein a distance between edges of the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 200 nm.