SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND ELECTRONIC DEVICE

• US 20120025268A1
• Filed: 10/05/2011
• Published: 02/02/2012
• Est. Priority Date: 04/07/2009
• Status: Active Grant

• Current Assignee: Sumitomo Chemical Company Limited
• Original Assignee: Sumitomo Chemical Company Limited
• Inventors: ICHIKAWA, Osamu
• Granted Patent: US 8,987,782 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: H01L 29/7785 with more than one donor layer
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

There is provided a compound semiconductor wafer that is suitably used as a semiconductor wafer to form a plurality of different types of devices such as an HBT and an FET thereon. The semiconductor wafer includes a first semiconductor, a carrier-trapping layer that is formed on the first semiconductor and has an electron-trapping center or a hole-trapping center, a second semiconductor that is epitaxially grown on the carrier-trapping layer and serves as a channel in which a free electron or a free hole moves, and a third semiconductor including a stack represented by n-type semiconductor/p-type semiconductor/n-type semiconductor or represented by p-type semiconductor/n-type semiconductor/p-type semiconductor, where the stack epitaxially grown on the second semiconductor.

Claims

1. A semiconductor wafer comprising:

a first semiconductor;

a carrier-trapping layer that is formed directly or indirectly on the first semiconductor and has an electron-trapping center or a hole-trapping center;

a second semiconductor that is epitaxially grown directly or indirectly on the carrier-trapping layer and serves as a channel in which a free electron or a free hole moves; and

a third semiconductor including a stack represented by n-type semiconductor/p-type semiconductor/n-type semiconductor or represented by p-type semiconductor/n-type semiconductor/p-type semiconductor, the stack epitaxially grown directly or indirectly on the second semiconductor.

2. The semiconductor wafer as set forth in claim 1, wherein

the first semiconductor contains a Group 3-5 compound semiconductor.

3. The semiconductor wafer as set forth in claim 1, further comprising

a depleted semiconductor that is disposed between the carrier-trapping layer and the second semiconductor and includes a depleted region.

4. The semiconductor wafer as set forth in claim 3, wherein

the depleted semiconductor is not less than 0.3 μ

m and not more than 1.5 μ

m in thickness in the growth direction between the first semiconductor and the second semiconductor.

5. The semiconductor wafer as set forth in claim 3, wherein

the depleted semiconductor contains a plurality of Group 3-5 compound semiconductors, and

of the plurality of Group 3-5 compound semiconductors, two adjoining Group 3-5 compound semiconductors together form at least one heterojunction selected from the group consisting of a heterojunction between Al_xGa_1-xAs (0≦

x≦

1) and Al_yGa_1-yAs (0≦

y≦

1, x<

y), a heterojunction between Al_pIn_qGa_1-p-qP (0≦

p≦

1, 0≦

q≦

1) and Al_rIn_sGa_1-r-sP (0≦

r≦

1, 0≦

s≦

1, p<

r), and a heterojunction between Al_xGa_1-xAs (0≦

x≦

1) and Al_pIn_qGa_1-p-qP (0≦

p≦

1, 0≦

q≦

1).

6. The semiconductor wafer as set forth in claim 1, wherein

the carrier-trapping layer contains a boron atom or an oxygen atom.

7. The semiconductor wafer as set forth in claim 6, wherein

the carrier-trapping layer contains an oxygen atom and one of Al_xGa_1-xAs (0≦

x≦

1) and Al_pIn_qGa_1-p-qP (0≦

p≦

1, 0≦

q≦

1).

8. The semiconductor wafer as set forth in claim 6, wherein

the concentration of the oxygen atom is not less than 1×

10¹⁸ cm<sup>−

3</sup> and not more than 1×

10²⁰ cm<sup>−

3</sup>.

9. The semiconductor wafer as set forth in claim 1, wherein

at least one semiconductor of the second semiconductor and the third semiconductor contains carbon.

10. The semiconductor wafer as set forth in claim 1, wherein

at least one semiconductor of the second semiconductor and the third semiconductor contains silicon.

11. The semiconductor wafer as set forth in claim 1, wherein

the third semiconductor contains silicon with which the third semiconductor is doped in a high concentration.

12. The semiconductor wafer as set forth in claim 1, wherein

the third semiconductor includes a ballast resistance layer having a resistance that suppresses a current flowing through the n-type semiconductor/p-type semiconductor/n-type semiconductor or the p-type semiconductor/n-type semiconductor/p-type semiconductor.

13. The semiconductor wafer as set forth in claim 1, further comprising

a fourth semiconductor that is disposed between the second semiconductor and the third semiconductor and has a carrier of a conductivity type opposite to the conductivity type of the carrier in the second semiconductor.

14. The semiconductor wafer as set forth in claim 1, wherein

the carrier-trapping layer is not less than 0.1 μ

m and not more than 1.5 μ

m in thickness in the growth direction between the first semiconductor and the second semiconductor.

15. A method of producing a semiconductor wafer, comprising:

forming, directly or indirectly on a first semiconductor, a carrier-trapping layer that has an electron-trapping center or a hole-trapping center;

epitaxially growing, directly or indirectly on the carrier-trapping layer, a second semiconductor that is to serve as a channel in which a free electron or a free hole moves; and

epitaxially growing, directly or indirectly on the second semiconductor, a third semiconductor including a stack represented by n-type semiconductor/p-type semiconductor/n-type semiconductor or a stack represented by p-type semiconductor/n-type semiconductor/p-type semiconductor.

16. The method as set forth in claim 15 of producing a semiconductor wafer, further comprising:

prior to the formation of the carrier-trapping layer, placing, within a reaction chamber, a wafer that has the first semiconductor at least on a surface thereof;

after the wafer has been placed within the reaction chamber, introducing a gas containing arsine and hydrogen into the reaction chamber; and

heating the first semiconductor within an atmosphere of the gas.

17. The method as set forth in claim 16 of producing a semiconductor wafer, wherein

the gas contains arsine, hydrogen, and a p-type impurity gas containing an element or a compound containing a p-type impurity atom as a constituent.

18. The method as set forth in claim 17 of producing a semiconductor wafer, wherein

the p-type impurity gas includes a halogenated hydrocarbon gas.

19. The method as set forth in claim 18 of producing a semiconductor wafer, wherein

the halogenated hydrocarbon gas is CH_nX_(4-n), wherein each X denotes a halogen atom selected from the group consisting of Cl, Br and I, n denotes an integer satisfying the condition of 0≦

n≦

3, and the atoms X may be either identical atoms or different atoms when 0≦

n≦

2.

20. The method as set forth in claim 17 of producing a semiconductor wafer, wherein

the third semiconductor includes a semiconductor layer that serves as a base of a bipolar transistor, and

the p-type impurity gas is a gas of the same type as a gas containing a dopant to be introduced in the production of the semiconductor layer that serves as the base.

21. The method as set forth in claim 15 of producing a semiconductor wafer, further comprising

forming, directly or indirectly on the carrier-trapping layer, a depleted semiconductor including a depleted region with the concentration of an acceptor being controlled by regulating the molar supply ratio of a Group 5 source to a Group 3 source.

22. The method as set forth in claim 16 of producing a semiconductor wafer, wherein

the gas includes an arsine source gas containing 1 ppb or less of GeH₄.

23. The method as set forth in claim 15 of producing a semiconductor wafer, wherein

during epitaxial growth of a layer for supplying a carrier to the second semiconductor, silane or disilane is introduced as a compound containing an n-type impurity atom that exhibits n-type conductivity, thereby epitaxially growing the layer for supplying the carrier, and

during the formation of the third semiconductor, silane or disilane is introduced as a compound containing an n-type impurity atom that exhibits n-type conductivity, thereby epitaxially growing the n-type semiconductor contained in the third semiconductor.

24. The method as set forth in claim 15 of producing a semiconductor wafer, further comprising

epitaxially growing, directly or indirectly on the second semiconductor, a fourth semiconductor that is to serve as a channel in which a carrier of a conductivity type opposite to the conductivity type of the carrier that moves in the second semiconductor moves.

25. The method as set forth in claim 16 of producing a semiconductor wafer, further comprising

after the formation of the third semiconductor, removing the wafer on which the second semiconductor and the third semiconductor have been formed from the reaction chamber, wherein

the removal, the placement of the wafer, the introduction of the gas, the heating, the formation of the carrier-trapping layer, the epitaxial growth of the second semiconductor and the formation of the third semiconductor are repeatedly performed.

26. An electronic device comprising:

a first semiconductor;

a carrier-trapping layer formed directly or indirectly on the first semiconductor;

a second semiconductor that is epitaxially grown directly or indirectly on the carrier-trapping layer and serves as a channel in which a free electron or a free hole moves;

a third semiconductor including a stack represented by n-type semiconductor/p-type semiconductor/n-type semiconductor or represented by p-type semiconductor/n-type semiconductor/p-type semiconductor, the stack epitaxially grown directly or indirectly on the second semiconductor;

a field-effect transistor formed in the second semiconductor; and

a heterojunction bipolar transistor formed in the third semiconductor.