Semiconductor Device Cover Mark

• US 20120025368A1
• Filed: 07/30/2010
• Published: 02/02/2012
• Est. Priority Date: 07/30/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Jing-Cheng, Chiou, Wen-Chih, Jeng, Shin-Puu, Yu, Chen-Hua, Lin, Yan-Fu
• Granted Patent: US 8,629,568 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2223/54413 comprising digital information, e.g. bar codes, data matrix
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/8113 : using marks formed on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81132 : using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate.

Claims

1. A device comprising:

a substrate having a first surface, the substrate comprising a region of attachment, the region of attachment having one or more contact pads; and

one or more cover marks along the first surface, the one or more cover marks comprising an indication of distance away from the region of attachment.

2. The semiconductor device of claim 1, further comprising:

a semiconductor substrate comprising one or more contact bumps, the contact bumps in contact with the contact pads; and

an underfill material between the semiconductor substrate and the substrate, the underfill material extending over at least a portion of the one or more cover marks.

3. The semiconductor device of claim 2, further comprising one or more semiconductor substrate cover marks located on the semiconductor substrate, the one or more semiconductor substrate cover marks being aligned with respective ones of the one or more cover marks.

4. The semiconductor device of claim 1, wherein the one or more cover marks further comprise:

a straight line extending perpendicularly away from a side of the region of attachment; and

hash marks extending away from the straight line parallel with the side of the region of attachment.

5. The semiconductor device of claim 1, wherein the one or more cover marks comprise an “

L”

shaped cover mark located adjacent to a corner of the region of attachment.

6. The semiconductor device of claim 1, wherein the one or more cover marks comprise a scale.

7. The semiconductor device of claim 1, wherein the one or more cover marks comprise numbers.

8. The semiconductor device of claim 1, wherein the one or more cover marks comprise rectangular marks that surround the region of attachment.

9. The semiconductor device of claim 1, wherein the one or more cover marks comprise dummy contact bumps.

10. A semiconductor device comprising:

a substrate with a first surface, the substrate comprising a first cover mark located around a first region of the first surface; and

a semiconductor substrate attached to the first region, the semiconductor substrate comprising a second cover mark aligned with the first cover mark and located along a second surface facing away from the first surface.

11. The semiconductor device of claim 10, further comprising an underfill material located between the semiconductor substrate and the substrate, the underfill material extending away from the semiconductor substrate and covering at least a portion of the first cover mark.

12. The semiconductor device of claim 10, further comprising a third cover mark, a fourth cover mark, and a fifth cover mark located on the first surface of the substrate, the first cover mark, third cover mark, fourth cover mark, and fifth cover mark each being located adjacent to a separate side of the first surface.

13. The semiconductor device of claim 12, wherein each of the third cover mark, the fourth cover mark, and the fifth cover mark are aligned with respective ones of a plurality of cover marks located on the substrate.

14. The semiconductor device of claim 10, wherein the first cover mark comprises a straight line intersecting a series of hash marks.

15. A method of manufacturing a semiconductor device, the method comprising:

providing a substrate;

forming a first cover mark on a first surface of the substrate;

placing a semiconductor substrate over the first surface of the substrate; and

placing an underfill material between the substrate and the semiconductor substrate, the underfill material extending towards the first cover mark from the region between the substrate and the semiconductor substrate.

16. The method of claim 15, further comprising determining a distance the underfill material extends from the semiconductor substrate using the first cover mark.

17. The method of claim 15, further comprising:

forming a second cover mark on a second surface of the semiconductor substrate; and

aligning the semiconductor substrate such that the second surface faces away from the first surface and the second cover mark on the second surface is aligned with the first cover mark on the first surface.

18. The method of claim 15, wherein the forming the first cover mark further comprises forming a first contact pad on the first surface simultaneously as the forming the first cover mark.

19. The method of claim 15, wherein the forming a first cover mark further comprising forming a scale.

20. The method of claim 15, wherein the forming a first cover mark further comprises forming reference numbers on the first surface.