Devices Formed With Dual Damascene Process
First Claim
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1. A semiconductor device comprising multiple levels of metallization, at least one metallization level comprising:
- a first metal level overlying a via level, the first metal level comprising metal lines embedded in an insulating layer; and
vias disposed in the via level, and disposed underneath the first metal level, wherein a top width of the metal lines in a region overlying the vias is about the same as a top width of the metal lines in a region not overlying the vias.
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Abstract
Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.
32 Citations
25 Claims
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1. A semiconductor device comprising multiple levels of metallization, at least one metallization level comprising:
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a first metal level overlying a via level, the first metal level comprising metal lines embedded in an insulating layer; and vias disposed in the via level, and disposed underneath the first metal level, wherein a top width of the metal lines in a region overlying the vias is about the same as a top width of the metal lines in a region not overlying the vias. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An interconnect structure comprising:
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a first metal line disposed in a first insulating layer; a second insulating layer disposed on the first insulating layer; a first via disposed in the second insulating layer, the first via disposed on the first metal line; and a second metal line disposed in the second insulating layer, wherein at least a portion of the second metal line is disposed on the first via, and wherein a bottom critical dimension (CD) of the second metal line in a region overlying the first via is about the same as a top CD of the first via. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. An interconnect structure comprising:
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a first metal line disposed in a first insulating layer; a second insulating layer disposed on the first insulating layer; a first via disposed in the second insulating layer, the first via disposed on the first metal line; and a second metal line disposed in the second insulating layer, wherein at least a portion of the second metal line is disposed on the first via, and wherein a top view of the first via comprises four sides, wherein two of the four sides comprise an arc shape along a width of the second metal line and the remaining two of the four sides along a length of the second metal line are linear, the length being longer than the width, wherein the length and width are measured along a surface parallel to a top surface of the first insulating layer. - View Dependent Claims (22, 23, 24, 25)
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Specification