Hermetic Wafer Level Packaging

• US 20120025389A1
• Filed: 07/29/2010
• Published: 02/02/2012
• Est. Priority Date: 07/29/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chu, Richard, Liu, Martin, Chu, Chia-Hua, Hsieh, Yuan-Chih, Lin, Chung-Hsien, Chao, Lan-Lin, Cheng, Chun-Wen, Liu, Mingo
• Granted Patent: US 8,648,468 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.

Claims

1. An apparatus, comprising:

a first substrate having a first bonding pad, the first bonding pad including a first material; and

a second substrate having a second bonding pad, the second bonding pad including a second material different from the first material, one of the first and second materials being aluminum, and the other thereof being a titanium alloy;

wherein a portion of the second substrate is bonded to the first substrate through the first and second bonding pads.

2. The apparatus of claim 1, wherein:

the first substrate includes an integrated circuit device; and

the second substrate includes one of;

a through-silicon via (TSV) and a micro-electrical-mechanical system (MEMS) device.

3. The apparatus of claim 2, wherein the second bonding pad is electrically coupled to the TSV.

4. The apparatus of claim 1, wherein the titanium alloy has a chemical composition of Ti_xAl_yCu_z, wherein x, y, and z are each in a range from 0 to 100.

5. The apparatus of claim 1, wherein the first substrate has a third bonding pad that includes a third material;

and further including a third substrate having a fourth bonding pad that includes a fourth material different from the third material, one of the third and fourth materials being aluminum, and the other thereof being a titanium alloy;

wherein;

the first and third substrates are bonded together through the third and fourth bonding pads; and

the portion of the second substrate is surrounded by the first and third substrates.

6. The apparatus of claim 1, wherein:

the first substrate has an interconnect structure that includes a plurality of metal interconnect features; and

the first bonding pad is one of the metal interconnect features.

7. A wafer level packaging, comprising:

a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material; and

a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based;

wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.

8. The packaging of claim 7, wherein the first wafer has a third bonding layer that includes a third material;

and further including a capping layer having a fourth bonding layer that includes a fourth material different from the third material, one of the third and fourth materials being aluminum-based, and the other thereof being titanium-based; and

wherein the first wafer and the capping layer are bonded together through the third and fourth bonding layers.

9. The packaging of claim 8, wherein the second wafer includes a micro-electrical-mechanical system (MEMS) device that is hermetically sealed by the capping layer and the first wafer.

10. The packaging of claim 7, wherein the titanium-based material is an alloy made of materials selected from the group consisting of:

titanium, aluminum, copper, and germanium.

11. The packaging of claim 7, wherein:

the second wafer has a through-silicon via that extends through the second wafer; and

the second bonding layer is coupled to the second bonding layer.

12. The packaging of claim 7, wherein the first wafer has an interconnect structure that includes a top metal layer, the first bonding layer being a portion of the top metal layer.

13. A method of packaging, comprising:

providing a first semiconductor wafer and a second semiconductor wafer;

forming a first bonding pad on the first wafer, the first bonding pad including a first bonding material;

forming a second bonding pad on the second wafer, the second bonding pad including a second material different from the first material, one of the first and second materials being aluminum, and the other thereof being a titanium alloy; and

bonding the first and second wafers together through the first and second bonding pads.

14. The method of claim 13, wherein the bonding is carried out using a metal diffusion process that includes:

a process temperature that is greater than approximately 100 degrees Celsius;

a process pressure that is greater than approximately 10 kilo-newtons; and

a process duration that is in a range from approximately 3 minutes to approximately 300 minutes.

15. The method of claim 13, further including:

after the bonding, annealing the first and second wafers at a temperature in a range from approximately 200 degrees Celsius to approximately 500 degrees Celsius for a duration in a range from approximately 0.5 hours to approximately 6 hours.

16. The method of claim 13, wherein:

the forming one of the first and second bonding pads having the titanium alloy is carried out using a process selected from the group consisting of;

physical vapor deposition, chemical vapor deposition, evaporation, electron beam gun, ion beam, energy beam, and plating; and

the titanium alloy has a chemical composition of Ti_xAl_yCu_z, x, y, and z each being in a range from 0 to 100.

17. The method of claim 13, further including:

providing a third wafer;

forming a third bonding pad on the first wafer, the third bonding pad including a third material;

forming a fourth bonding pad on the third wafer, the fourth bonding pad having a fourth material different from the third material, one of the third and fourth materials being aluminum, and the other thereof being a titanium alloy; and

after the bonding the first and second wafers, bonding the first and third wafers together through the third and fourth bonding pads.

18. The method of claim 17, wherein:

the first wafer has a transistor;

the second wafer has a micro-electrical-mechanical system (MEMS) device; and

the third wafer is a capping layer.

19. The method of claim 13, wherein:

the providing the first wafer is carried out in a manner so that the first wafer has an interconnect structure that includes a plurality of metal interconnect features; and

the forming the first bonding pad is carried out in a manner so that the first bonding pad is one of the metal interconnect features.

20. The method of claim 13, wherein:

the providing the second wafer is carried out in a manner so that the second wafer includes a through-silicon via (TSV); and

the forming the second bonding pad is carried out in a manner so that the second bonding pad is electrically coupled to the TSV.