TEST SOCKET AND TEST DEVICE HAVING THE SAME

• US 20120025861A1
• Filed: 08/02/2011
• Published: 02/02/2012
• Est. Priority Date: 08/02/2010
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, Hwan Wook, KIM, Woo Seop, CHO, Sung Bum
• Application Number:
  US13/196,380
• Publication Number:
  US 20120025861A1
• Time in Patent Office: Days
• US Class Current: 324/756.02
• CPC Class Codes: G01R 1/045 Sockets or component fixtures for RF or HF testing
• CPC Class Codes: G01R 1/0466 concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding

Abstract

A test device is provided. The test device includes a first via which transmits a supply voltage, a second via which transmits a ground voltage, a test board including a plurality of test signal vias for transmitting a plurality of test signals, a capacitor disposed on an upper part of the test board and connected between the first via and the second via, and a test socket which electrically connects a device under test (DUT) with the test board. The test socket includes a first region including a flat lower surface bordering the test board, a second region including an uneven lower surface, a plurality of first contactors which are disposed in the first region and which are connected to the plurality of vias, and two second contactors which are disposed in the second region and which are connected to two terminals of the capacitor.

Claims

1. A test socket for a semiconductor memory device which electrically connects a device under test (DUT) with a test board, the test socket comprising:

a frame comprising a first region comprising a flat lower surface, and a second region comprising an uneven lower surface;

a plurality of first contactors which are disposed in the first region and which supply a plurality of test signals output from the test board to the DUT; and

a plurality of second contactors which are disposed in the second region and which supply a plurality of voltages output from the test board to the DUT.

2. The test socket of claim 1, wherein a length of each of the plurality of first contactors is longer than a length of each of the plurality of second contactors.

3. The test socket of claim 1, wherein each of the plurality of first contactors and each of the plurality of second contactors comprises is a Pogo pin.

4. The test socket of claim 1, wherein each of the plurality of first contactors and each of the plurality of second contactors comprises a conductive rubber.

5. A test device for a semiconductor memory device comprising:

a test board comprising a first via which transmits a supply voltage, a second via which transmits a ground voltage and a plurality of test signal vias which transmit a plurality of test signals;

a capacitor which is disposed on an upper portion of the test board and which is connected between the first via and the second via; and

a test socket which electrically connects a device under test (DUT) with the test board,

wherein the test socket comprises;

a frame comprising a first region comprising a flat lower surface, and a second region comprising an uneven lower surface;

a plurality of first contactors which are disposed in the first region, wherein each of the plurality of first contactors is connected to one of the plurality of test signal vias; and

two second contactors which are disposed in the second region, each of which is connected to a terminal of the capacitor.

6. The test device of claim 5, wherein a length of each of the plurality of first contactors is longer than a length of each of the two second contactors.

7. The test device of claim 5, wherein each of the plurality of first contactors and each of the two second contactors comprises a Pogo pin.

8. The test device of claim 5, wherein each of the plurality of first contactors and each of the two second contactors comprises a conductive rubber.

9. A test socket for a semiconductor memory device which electrically connects a device under test (DUT) with a test board, the test socket comprising:

a lower region comprising a plurality of first contactors which are disposed to electrically contact the test board;

an upper region comprising a plurality of second contactors which are disposed to electrically contact the DUT; and

a printed circuit board (PCB) which is disposed between the upper region and the lower region, and which comprises a plurality of vias and a capacitor comprising two terminals,

wherein each of the terminals of the capacitor and each of the vias is connected to one of the plurality of first contactors and one of the plurality of second contactors.

10. The test socket of claim 9, wherein each of the plurality of first contactors and each of the plurality of second contactors comprises a conductive rubber.

11. A test device for a semiconductor memory device comprising:

a test board;

a device under test (DUT); and

a test socket which electrically connects the test board to the DUT,

wherein the test socket comprises;

a lower region comprising a plurality of first contactors which are electrically connected to the test board;

an upper region comprising a plurality of second contactors which are electrically connected to the DUT; and

a printed circuit board (PCB) which is disposed between the upper region and the lower region, and which comprises a plurality of vias and a capacitor comprising two terminals,

wherein each of the terminals of the capacitor and each of the vias is connected to one of the plurality of first contactors and one of the plurality of second contactors.

12. The test device of claim 11, wherein each of the plurality of first contactors and each of the plurality of second contactors comprises a conductive rubber.

13. (canceled)

14. (canceled)