PARALLEL ARRAY ARCHITECTURE FOR A GRAPHICS PROCESSOR
First Claim
1. A graphics processor comprising:
- a multithreaded core array including a plurality of processing clusters; and
a crossbar configured to connect the plurality of processing clusters to a frame buffer configured to store data associated with pixels of an image, the frame buffer being partitioned into a plurality of partitions,wherein each processing cluster includes;
a set of one or more processing cores operable to execute programs;
a pixel module configured to receive coverage data and to direct at least one of the processing cores to execute a pixel shader program on the received coverage data to generate pixel values; and
a raster operations unit configured to receive the pixel values generated by the at least one processing core and to update the pixel data stored in the frame buffer based on the received pixel values, andwherein the raster operations unit of each processing cluster is coupled to the crossbar such that every partition of the frame buffer is accessible to every one of the raster operations units.
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Abstract
A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.
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Citations
17 Claims
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1. A graphics processor comprising:
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a multithreaded core array including a plurality of processing clusters; and a crossbar configured to connect the plurality of processing clusters to a frame buffer configured to store data associated with pixels of an image, the frame buffer being partitioned into a plurality of partitions, wherein each processing cluster includes; a set of one or more processing cores operable to execute programs; a pixel module configured to receive coverage data and to direct at least one of the processing cores to execute a pixel shader program on the received coverage data to generate pixel values; and a raster operations unit configured to receive the pixel values generated by the at least one processing core and to update the pixel data stored in the frame buffer based on the received pixel values, and wherein the raster operations unit of each processing cluster is coupled to the crossbar such that every partition of the frame buffer is accessible to every one of the raster operations units. - View Dependent Claims (2, 3, 4)
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5. A graphics processor comprising:
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a multithreaded core array including a plurality of processing clusters; a rasterizer configured to generate coverage data for each of a plurality of pixels; pixel distribution logic configured to deliver a portion of the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array; and a crossbar connecting the plurality of processing clusters to a frame buffer configured to store pixels of an image, the frame buffer being partitioned into a plurality of partitions, wherein each processing cluster includes; a set of one or more processing cores operable to execute program instructions; a pixel module configured to receive a portion of the coverage data from the rasterizer and to direct at least one of the processing cores to execute a pixel shader program on the received coverage data to generate pixel values; and a raster operations unit configured to receive the pixel values generated by the at least one processing core and to combine the received pixel values with pixels of an image in the frame buffer, and wherein the raster operations unit of each processing cluster is coupled to the crossbar such that every partition of the frame buffer is accessible to every one of the raster operations units. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A graphics processor comprising:
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a multithreaded core array including a plurality of processing clusters; and a crossbar configured to connect the plurality of processing clusters to a plurality of frame buffers, each of the plurality of frame buffers being configured to store data for a different attribute associated with pixels of an image, each of the plurality of frame buffers being partitioned into a plurality of partitions, wherein each processing cluster includes; a set of one or more processing cores operable to execute programs; a pixel module configured to receive coverage data and to direct at least one of the processing cores to execute a pixel shader program on the received coverage data to generate pixel values; and a raster operations unit configured to receive the pixel values generated by the at least one processing core and to update the pixel data stored in the frame buffer based on the received pixel values, and wherein the raster operations unit of each processing cluster is coupled to the crossbar such that every partition of each one of the frame buffers is accessible to every one of the raster operations units. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification