SEMICONDUCTOR STORAGE DEVICE
First Claim
Patent Images
1. A semiconductor storage device comprising:
- a memory cell array including a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells arranged at intersections between the first lines and the second lines and each including a variable resistive element; and
a control circuit which controls resistance values of the variable resistive elements in such a way that a cell voltage is applied to the memory cell arranged at an intersection between a selected one of the plurality of first lines and a selected one of the plurality of second lines by applying a first voltage to the selected first line and by applying a second voltage to the selected second line, whereinthe control circuit applies a voltage gradually raised or lowered from a first initial voltage as the first voltage to the selected first line, and applies a pulsing voltage as the second voltage to the selected second line, andthe second voltage includes a voltage pulse which is raised from a second initial voltage which the memory cell is a non-selected state to a raised voltage which the memory cell is a selected state, is kept at the raised voltage to thereby cause a cell current to flow into the memory cell, and is lowered to the second initial voltage when the cell current that increases while the voltage of the memory cell is rising with a change in the first voltage reaches a compliance current.
5 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor memory device includes: a memory cell array including multiple first lines, multiple second lines crossing the first lines, and memory cells arranged at intersections between the first lines and the second lines and including variable resistive elements; and a control circuit which controls resistance values of the variable resistive elements in a way that a cell voltage is applied to the memory cell arranged at an intersection between a selected first line and a selected second line by applying first and second voltages to the selected first and second lines, respectively. The control circuit applies a voltage gradually raised or lowered from a first initial voltage as the first voltage to the selected first line, and a pulsing voltage as the second voltage to the selected second line. The second voltage includes a voltage pulse which is raised from a second initial voltage to turn the memory cell into a non-selected state to a voltage to turn the memory cell into a selected state, is kept at the raised voltage to thereby cause a cell current to flow into the memory cell, and is lowered to the second initial voltage when the cell current that increases while the voltage of the memory cell is rising with a change in the first voltage reaches a predetermined compliance current.
-
Citations
15 Claims
-
1. A semiconductor storage device comprising:
-
a memory cell array including a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells arranged at intersections between the first lines and the second lines and each including a variable resistive element; and a control circuit which controls resistance values of the variable resistive elements in such a way that a cell voltage is applied to the memory cell arranged at an intersection between a selected one of the plurality of first lines and a selected one of the plurality of second lines by applying a first voltage to the selected first line and by applying a second voltage to the selected second line, wherein the control circuit applies a voltage gradually raised or lowered from a first initial voltage as the first voltage to the selected first line, and applies a pulsing voltage as the second voltage to the selected second line, and the second voltage includes a voltage pulse which is raised from a second initial voltage which the memory cell is a non-selected state to a raised voltage which the memory cell is a selected state, is kept at the raised voltage to thereby cause a cell current to flow into the memory cell, and is lowered to the second initial voltage when the cell current that increases while the voltage of the memory cell is rising with a change in the first voltage reaches a compliance current. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A semiconductor storage device comprising:
-
a memory cell array including a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells arranged at intersections between the first lines and the second lines and each including a variable resistive element; and a control circuit which controls resistance values of the variable resistive elements in such a way that a cell voltage is applied to the memory cells arranged at an intersection between a selected one of the first lines and a first-selected one of the second lines and at an intersection between the selected first line and a second-selected one of the second lines by applying a first voltage to the selected first line, by applying a second voltage to the first-selected second line, and by applying a third voltage to the second-selected second line, wherein the control circuit applies a voltage gradually raised or lowered from a first initial voltage as the first voltage to the selected first line, applies a pulsing voltage as the second voltage to the first-selected second line, and applies a pulsing voltage as the third voltage to the second-selected second line, and the second voltage includes a voltage pulse which is raised from a second initial voltage which the memory cell is a non-selected state of the memory cell to a voltage which the memory cell is a selected state, is kept at the raised voltage to thereby cause a cell current to flow into the memory cell, and is lowered to the second initial voltage when the cell current that increases while the voltage of the memory cell is rising along with a change in the first voltage reaches a compliance current, and the third voltage includes a voltage pulse which is raised from the second initial voltage which the memory cell is the non-selected state to the voltage which the memory cell is the selected state of the memory cell, is kept at the raised voltage to thereby cause a cell current to flow into the memory cell, and is lowered to the second initial voltage when the cell current that increases while the voltage of the memory cell is rising with the change in the first voltage reaches a compliance current. - View Dependent Claims (10, 11, 12, 13, 14, 15)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeKioxia Corporation
-
Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
-
InventorsMAEJIMA, Hiroshi
-
Granted Patent
-
Time in Patent OfficeDays
-
Field of Search
-
US Class Current365/148
-
CPC Class CodesG11C 13/0004 comprising amorphous/crysta...G11C 13/0007 comprising metal oxide memo...G11C 13/0011 comprising conductive bridg...G11C 13/0023 Address circuits or decodersG11C 13/0026 Bit-line or column circuitsG11C 13/0028 Word-line or row circuitsG11C 13/0038 Power supply circuitsG11C 13/004 Reading or sensing circuits...G11C 13/0069 Writing or programming circ...G11C 2013/0066 Verify correct writing whil...G11C 2013/0083 Write to perform initialisi...G11C 8/08 Word line control circuits,...
