Methods for Manufacturing Arrays for CMOS Imagers

• US 20120028401A1
• Filed: 08/01/2011
• Published: 02/02/2012
• Est. Priority Date: 08/02/2010
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: De Vos, Joeri, De Munck, Koen, Minoglou, Kiki
• Granted Patent: US 8,530,264 B2
• Time in Patent Office: Days
• US Class Current: 438/73
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00

Abstract

Methods of fabricating complementary metal-oxide-semiconductor (CMOS) imagers for backside illumination are disclosed. In one embodiment, the method may include forming at a front side of a substrate a plurality of high aspect ratio trenches having a predetermined trench depth, and forming at the front side of the substrate a plurality of photodiodes, where each photodiode is adjacent at least one trench. The method may further include forming an oxide layer on inner walls of each trench, removing the oxide layer, filling each trench with a highly doped material, and thinning the substrate from a back side opposite the front side to a predetermined final substrate thickness. In some embodiments, the substrate may have a predetermined doping profile, such as a graded doping profile, that provides a built-in electric field suitable to guide the flow of photogenerated minority carriers towards the front side.

Claims

1. A method comprising:

forming at a front side of a substrate a plurality of high aspect ratio trenches having a predetermined trench depth;

forming at the front side of the substrate a plurality of photodiodes, wherein each photodiode is adjacent at least one trench;

forming an oxide layer on inner walls of each trench;

removing the oxide layer;

filling each trench with a highly doped material; and

thinning the substrate from a back side opposite the front side to a predetermined final substrate thickness.

2. The method of claim 1, wherein each trench has a depth at least ten times its width.

3. The method of claim 1, wherein the predetermined trench depth is greater than or equal to the predetermined final substrate thickness.

4. The method of claim 1, wherein the highly doped material comprises highly doped polysilicon.

5. The method of claim 1, further comprising:

forming at least one electrical contact at the front side.

6. The method of claim 1, further comprising:

forming a dielectric layer on the first side.

7. The method of claim 1, wherein forming each photodiode comprises:

forming a well at the front side; and

forming the photodiode adjacent to the well.

8. The method of claim 7, wherein each well has a conductivity opposite a conductivity of the substrate.

9. The method of claim 1, wherein forming the oxide layer comprises forming the oxide layer using at least one of in-situ steam generated oxidation, wet oxidation, dry oxidation, and rapid thermal oxidation.

10. The method of claim 1, further comprising performing a chemical mechanical polish after filling each trench with the highly doped material.

11. A method comprising:

providing a substrate having a predetermined doping profile;

forming at a front side of the substrate a plurality of high aspect ratio trenches having a predetermined trench depth;

forming at the front side of the substrate a plurality of photodiodes, wherein each photodiode is adjacent at least one trench;

forming an oxide layer on inner walls of each trench;

removing the oxide layer;

filling each trench with a highly doped material; and

thinning the substrate from a back side opposite the front side to a predetermined final substrate thickness.

12. The method of claim 11, wherein the predetermined doping profile comprises a graded doping profile.

13. The method of claim 12, wherein the graded doping profile provides a built-in electric field suitable to guide the flow of photogenerated minority carriers towards the front side.

14. The method of claim 12, wherein the graded doping profile comprises one of a continuous slope doping profile and a staircase doping profile.

15. The method according to claim 11, wherein providing the substrate comprises:

providing a sacrificial substrate; and

epitaxially growing a silicon layer with the predetermined doping profile on the sacrificial substrate to provide the graded doping profile.

16. The method of claim 11, wherein thinning the substrate comprises removing at least a portion of the sacrificial substrate.

17. A method of fabricating a plurality of complementary metal-oxide-semiconductor (CMOS) imagers for backside illumination, comprising:

forming at a front side of a substrate a plurality of high aspect ratio trenches having a predetermined trench depth;

forming at the front side of the substrate a plurality of photodiodes, wherein each photodiode is adjacent at least one trench;

forming an oxide layer on inner walls of each trench;

removing the oxide layer;

filling each trench with a highly doped material; and

thinning the substrate from a back side opposite the front side to a predetermined final substrate thickness.

18. The method of claim 17, further comprising:

performing a surface treatment on the back side.

19. The method of claim 17, further comprising:

integrating the CMOS imagers with a readout integrated circuit.

20. The method of claim 17, wherein the substrate has a predetermined doping profile.