SEMICONDUCTOR COMPONENT WITH CELL STRUCTURE AND METHOD FOR PRODUCING THE SAME

• US 20120028417A1
• Filed: 10/07/2011
• Published: 02/02/2012
• Est. Priority Date: 02/20/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hirler, Franz, Haeberlen, Oliver, Rieger, Walter
• Granted Patent: US 8,389,362 B2
• Time in Patent Office: Days
• US Class Current: 438/113
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor component comprises a semiconductor body comprising a first component electrode arranged on one of the surfaces of the semiconductor body, a second component electrode arranged on one of the surfaces of the semiconductor body, and a component control electrode arranged on one of the surfaces of the semiconductor body. In this case, active semiconductor element cells are arranged in a first active cell array of the semiconductor body, the semiconductor element cells comprising a first cell electrode, a second cell electrode and a cell control electrode and also a drift path between the cell electrodes. At least the component control electrode is arranged on a partial region of the semiconductor body and a second active cell array is additionally situated in the partial region of the semiconductor body below the component control electrode.

Claims

1. A method for producing a plurality of semiconductor chips for semiconductor components with cell structures, comprising:

patterning a semiconductor wafer composed of a monocrystalline semiconductor body with cell structures for MOSFETs, IGBTs or JFETs with a lateral or vertical drift path arranged between a first region of the semiconductor body for a first cell electrode and a second region of the semiconductor body for a second cell electrode, wherein the first region has a surrounding body zone with semiconductor material doped complementarily to the drift path, which body zone can be activated by a cell control electrode in interaction with a component control electrode;

arranging the cell structures in semiconductor chip positions to form a first active cell array provided below a first or a second component electrode; and

arranging the cell structures in at least one partial region of the semiconductor chip positions to form a second active cell array of the partial region, the array being provided below a component control electrode.

2. The method of claim 1, wherein arranging the cell structures comprises carrying out a strip-type introduction of trench structures at least for cell control electrodes both of the first cell array and of a second cell array of the partial region.

3. The method of claim 1, further comprising:

applying the semiconductor chips to a component carrier with a plurality of external contacts in a plurality of semiconductor device positions;

connecting the component electrodes of the semiconductor chips to contact pads which are electrically connected to the external contacts;

applying a semiconductor component housing and in the process enclosing the individual semiconductor chips and the connecting elements; and

separating the circuit carrier into individual semiconductor components.

4. The method of claim 1, wherein a plurality of cell control electrodes are introduced into the trench structure alongside one another or one below another.

5. The method of claim 1, wherein insulation materials or electrically conductive materials are selectively applied by photolithography.

6. The method of claim 1, wherein an anisotropic etch by a dry reactive ion etch is carried out for introducing trench structures.

7. The method of claim 1, wherein, as insulation interlayer between two metallization structures, one of the insulation materials from the group SiO₂, Si₃N₄ or polyimide is applied by using PVD or CVD.

8. The method of claim 1, wherein a highly doped electrically conductive polysilicon is deposited for filling the trench structures with a conductive cell control electrode material.

9. The method of claim 1, wherein a deposition of highly doped polysilicon is carried out for selectively depositing cell control electrode connecting lines.

10. The method of claim 1, wherein, as an alternative to producing plated-through holes to the body zones, a process of contact-connecting the body zones to the source zones of a MOSFET cell structure is carried out by sputtering a thin strip-type metallization layer onto the silicon surface of the semiconductor body.