DEFECT-FREE HETERO-EPITAXY OF LATTICE MISMATCHED SEMICONDUCTORS

• US 20120028444A1
• Filed: 07/29/2010
• Published: 02/02/2012
• Est. Priority Date: 07/29/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Vellianitis, Georgios
• Granted Patent: US 8,119,494 B1
• Time in Patent Office: Days
• US Class Current: 438/478
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02455 Group 13/15 materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02647 Lateral overgrowth

Abstract

A method includes providing a semiconductor substrate formed of a first semiconductor material; and forming a plurality of insulation regions over at least a portion of the semiconductor substrate, with a plurality of trenches separating the plurality of insulation regions apart from each other. A first epitaxial growth is performed to epitaxially grow a plurality of semiconductor regions in the plurality of trenches, wherein (111) facets are formed and exposed during the step of the first epitaxial growth. When the (111) facets of neighboring ones of the plurality of semiconductor regions touch each other, a second epitaxial growth is performed to continue grow the plurality of semiconductor regions to form (100) planes between the neighboring ones of the plurality of semiconductor regions.

Claims

1. A method comprising:

providing a semiconductor substrate comprising a first semiconductor material, wherein the first semiconductor material comprises silicon;

forming a plurality of insulation regions over at least a portion of the semiconductor substrate, with a plurality of trenches separating the plurality of insulation regions apart from each other;

performing a first epitaxial growth to epitaxially grow a plurality of semiconductor regions in the plurality of trenches, wherein (111) facets are formed and exposed during the step of the first epitaxial growth, wherein the plurality of semiconductor regions are germanium-containing regions;

at a time the (111) facets of neighboring ones of the plurality of semiconductor regions touch each other, performing a second epitaxial growth to continue growing the plurality of semiconductor regions to form (100) planes between the neighboring ones of the plurality of semiconductor regions; and

forming a dielectric region over portions of the plurality of insulation regions, wherein during the second growth, portions of the plurality of semiconductor regions that are over top surfaces of the plurality of insulation regions are confined by the dielectric region.

2. The method of claim 1, wherein the first epitaxial growth and the second epitaxial growth are performed using same process conditions.

3. The method of claim 1, wherein the first epitaxial growth and the second epitaxial growth are performed using different process conditions.

4. The method of claim 1, wherein during an entirety of the first epitaxial growth, process conditions are substantially not changed.

6. The method of claim 1, wherein each of the plurality of trenches has an aspect ratio greater than about 1.73.

7. The method of claim 6, wherein the aspect ratio is greater than about 3.46.

8. The method of claim 1, wherein the plurality of semiconductor regions are formed of substantially pure germanium.

9. The method of claim 1, wherein germane partial pressures in the first epitaxial growth and the second epitaxial growth are lower than about 0.13 Torr.

10. The method of claim 1, wherein growth temperatures of the first epitaxial growth and the second epitaxial growth are between about 500°

C. and about 650°

C.

11. The method of claim 1, wherein from a time when top ends of the plurality of semiconductor regions are level with a top surface of the plurality of insulation regions to a time when the neighboring ones of the plurality of semiconductor regions touch each other, substantially no (100) planes are formed.

21. The method of claim 1, wherein the semiconductor substrate is a silicon substrate, and the plurality of semiconductor regions is silicon germanium regions or substantially pure germanium regions.

5. (canceled)

12. A method comprising:

providing a silicon-containing semiconductor, substrate;

forming a plurality of insulation regions over at least a lower portion of the silicon-containing semiconductor substrate, with a plurality of trenches separating the plurality of insulation regions apart from each other; and

performing an epitaxial growth to epitaxially grow a plurality of semiconductor regions from trenches, until the plurality of semiconductor regions merge with each other to form a bulk semiconductor region having a substantially flat top surface, wherein the semiconductor regions comprise germanium, and wherein the epitaxial growth comprises;

a first epitaxial growth step ending at a time neighboring ones of the plurality of semiconductor regions touch each other, wherein process conditions for the first epitaxial growth step are configured to form (111) facets, with the (111) facets exposed on top ends of the plurality of semiconductor regions; and

a second epitaxial growth step starting at the time the neighboring ones of the plurality of semiconductor regions touch each other, wherein process conditions for the second epitaxial growth step are configured to form (100) planes between and connecting the neighboring ones of the plurality of semiconductor regions.

13. The method of claim 12, wherein at the time the neighboring ones of the plurality of semiconductor regions touch each other, the (111) facets of the neighboring ones of the plurality of semiconductor regions touch each other.

14. The method of claim 13, wherein germane flow rates in the first and the second epitaxial growth steps are between about 2.5 sccm and about 10 sccm, and wherein hydrogen flow rates in the first and the second epitaxial growth steps are between about 50 slm and about 100 slm.

15. The method of claim 13, wherein growth temperatures in the first and the second epitaxial growth steps are between about 500°

C. and about 650°

C.

16. The method of claim 12, wherein the semiconductor substrate comprises silicon, and wherein the plurality of semiconductor regions is formed of substantially pure germanium.

22. The method of claim 12, wherein the plurality of semiconductor regions is silicon germanium regions or substantially pure germanium regions.

17. A method comprising:

providing a silicon substrate;

forming a plurality of insulation regions over the silicon substrate, with a plurality of trenches separating the plurality of insulation regions apart from each other, wherein the plurality of insulation regions have substantially uniform spacings;

forming an additional insulation region over portions of the plurality of insulation regions, wherein the additional insulation region encircles a combined region comprising first regions and second regions, wherein the first regions are directly over the plurality of insulation regions, and the second region are directly over the plurality of trenches;

performing an epitaxial growth to epitaxially grow a plurality of germanium regions from trenches, wherein surfaces of the plurality of germanium regions are formed of substantially pure (111) facets; and

continuing the epitaxial growth after the (111) facets of the plurality of germanium regions touch each other until a block germanium region having a substantially flat top surface is formed in the region, wherein during the step of continuing the epitaxial growth, process conditions for growing the block germanium region are adjusted to form (100) planes.

19. The method of claim 17, wherein the plurality of trenches have uniform spacings.

20. The method of claim 17, wherein the plurality of trenches have aspect ratios greater than about 1.73.

18. (canceled)