INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD

• US 20120030405A1
• Filed: 03/31/2011
• Published: 02/02/2012
• Est. Priority Date: 07/30/2010
• Status: Active Grant

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Uemura, Goh, Owa, Tsutomu, KUNIMATSU, Atsushi
• Granted Patent: US 8,645,612 B2
• Time in Patent Office: Days
• US Class Current: 711/6
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 9/45537 Provision of facilities of other operating environments, e.g. WINE I/O emulation G06F13/105

Abstract

According to one embodiment, an information processing device includes an OS and a virtual machine switching section. The OS accesses a hardware resource including a nonvolatile semiconductor memory and a semiconductor memory used as a cache memory of the nonvolatile semiconductor memory. The virtual machine switching section switches a virtual machine in exection from a first virtual machine to a second virtual machine while a cache process is executed, when cache miss in a process executed by the first virtual machine is detected.

Claims

1. An information processing device comprising:

an operating system which accesses a hardware resource including a nonvolatile semiconductor memory and a semiconductor memory used as a cache memory of the nonvolatile semiconductor memory;

first and second virtual machines operating on the operating system;

a cache-miss detection section which detects cache miss to the semiconductor memory in a process executed by the first virtual machine;

a cache control section which executes a cache process when the cache-miss detection section detects the cache miss in the process; and

a virtual machine switching section which, when the cache-miss detection section detects the cache miss in the process executed by the first virtual machine, switches a virtual machine in execution from the first virtual machine to the second virtual machine while the cache control section executes the cache process.

2. The information processing device of claim 1, wherein the nonvolatile semiconductor memory is used as a main memory.

3. The information processing device of claim 1, further comprising:

first and second guest operating systems operating on each of the first and second virtual machines; and

an allocation determination section which determines an allocation area of data in at least one of the nonvolatile semiconductor memory and the semiconductor memory when writing the data, wherein

the first and second guest operating systems generate access frequency information on the data, the data being processed in the process executed on the operating system, and

the allocation determination section determines the allocation area of the data based on the access frequency information.

4. The information processing device of claim 3, wherein

the allocation determination section determines the allocation area based on the access frequency information and each degree of wear of memory area in the nonvolatile semiconductor memory.

5. The information processing device of claim 1, further comprising control software which is executed by a processor, the control software controlling the nonvolatile semiconductor memory to use as an auxiliary memory, and determining an allocation area of each data based on a file allocation table associated with the nonvolatile semiconductor memory or access frequency information of each data.

6. The information processing device of claim 1, wherein

the virtual machine switching section comprises a management table managing an execution status of each of the first and second virtual machines, a time for enable, and a priority of execution, and switches the virtual machine in execution based on the management table.

7. The information processing device of claim 1, wherein

the nonvolatile semiconductor memory includes a NAND flash memory of Single Level Cells and a NAND flash memory of Multi Level Cells.

8. The information processing device of claim 1, wherein

the semiconductor memory is a volatile semiconductor memory.

9. The information processing device of claim 1, wherein the operating system selects process switching when a time required for the cache process is shorter than or equal to a reference time, and selects virtual machine switching when the time required for the cache process is longer than the reference time.

10. The information processing device of claim 1, wherein the operating system selects thread switching when a time required for the cache process is shorter than or equal to a reference time, and selects virtual machine switching when the time required for the cache process is longer than the reference time.

11. An information processing method comprising:

operateing first and second virtual machines on an operating system which accesses a hardware resource including a nonvolatile semiconductor memory and a semiconductor memory used as a cache memory of the nonvolatile semiconductor memory, by a processor;

detecting, by at least one of the processor and a memory management device, cache miss to the semiconductor memory in a process executed by the first virtual machine and, when the cache miss is detected, executes a cache process; and

switching a virtual machine in execution from the first virtual machine to the second virtual machine while the cache process is executed, by the at least one of the processor and the memory management device.

12. The information processing method of claim 11, wherein the nonvolatile semiconductor memory is used as a main memory.

13. The information processing method of claim 11, further comprising:

determining an allocation area of data in at least one of the nonvolatile semiconductor memory and the semiconductor memory, by the at least one of the processor and the memory management device, wherein

each of the first and second virtual machines operate first and second guest operating systems,

the first and second guest operating systems generate access frequency information on the data, the data being processed in the process executed on the operating system, and

the determining the allocation area determines the allocation area of the data based on the access frequency information.

14. The information processing method of claim 11, further comprising:

executing, by a processor, control software determining an allocation area of each data based on a file allocation table associated with the nonvolatile semiconductor memory or access frequency information of each data, the control software controlling the nonvolatile semiconductor memory to use as an auxiliary memory.

15. The information processing method of claim 11, wherein

the switching refers a management table managing an execution status of each of the first and second virtual machines, a time for enable, and a priority of execution, and switches the virtual machine in execution based on the management table.

16. The information processing method of claim 11, wherein the operating system selects process switching when a time required for the cache process is shorter than or equal to a reference time, and selects virtual machine switching when the time required for the cache process is longer than the reference time.

17. The information processing method of claim 11, wherein the operating system selects thread switching when a time required for the cache process is shorter than or equal to a reference time, and selects virtual machine switching when the time required for the cache process is longer than the reference time.