PREDICTIVE SEQUENTIAL PREFETCHING FOR DATA CACHING
First Claim
1. A method for prefetching memory in caching systems, comprising:
- receiving a request for a memory line having an associated address;
allocating memory space for storing a first adjacent memory line that has an associated address that is adjacent to the associated address of the requested memory line;
accessing a prefetch indicator associated with the requested memory line to determine whether the first adjacent memory line has been prefetched; and
in response to a determination of the accessed prefetch indicator that the first adjacent memory has not been prefetched, prefetching the first adjacent memory line and storing an indication in the prefetch indicator associated with the requested memory line that the first adjacent memory line has been prefetched.
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Accused Products
Abstract
A system for prefetching memory in caching systems includes a processor that generates requests for data. A cache of a first level stores memory lines retrieved from a lower level memory in response to references to addresses generated by the processor'"'"'s requests for data. A prefetch buffer is used to prefetch an adjacent memory line from the lower level memory in response to a request for data. The adjacent memory line is a memory line that is adjacent to a first memory line that is associated with an address of the request for data. An indication that a memory line associated with an address associated with the requested data has been prefetched is stored. A prefetched memory line is transferred to the cache of the first level in response to the stored indication that a memory line associated with an address associated with the requested data has been prefetched.
45 Citations
20 Claims
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1. A method for prefetching memory in caching systems, comprising:
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receiving a request for a memory line having an associated address; allocating memory space for storing a first adjacent memory line that has an associated address that is adjacent to the associated address of the requested memory line; accessing a prefetch indicator associated with the requested memory line to determine whether the first adjacent memory line has been prefetched; and in response to a determination of the accessed prefetch indicator that the first adjacent memory has not been prefetched, prefetching the first adjacent memory line and storing an indication in the prefetch indicator associated with the requested memory line that the first adjacent memory line has been prefetched. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for prefetching memory in caching systems, comprising:
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accessing a prefetch indicator associated with a requested memory line or a memory line adjacent to the requested memory line to determine whether the requested memory line has been prefetched; in response to a determination of the accessed prefetch indicator that the requested memory line has been prefetched, transferring the prefetched requested memory line to a first level cache; in response to a determination of the accessed prefetch indicator that the requested memory line has not been prefetched, transferring the requested memory line from a lower level memory to a first level cache; and in response to a determination of the accessed prefetch indicator that the first adjacent memory has not been prefetched, prefetching the first adjacent memory line and storing an indication in the prefetch indicator associated with the requested memory line that the first adjacent memory line has been prefetched. - View Dependent Claims (14)
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15. A system for prefetching memory in caching systems, comprising:
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a processor that is configured to generate requests for data, wherein each request for data has an associated address that is included within at least one memory line; a cache of a first level configured to store memory lines from a lower level memory, wherein each memory line is associated with at least one memory address of a request for data; a prefetch buffer configured to prefetch an adjacent memory line from the lower level memory in response to the request for data wherein the adjacent memory line is a memory line that is adjacent to a first memory line that at least includes an address associated with the request for data, to store an indication that a memory line associated with an address associated with the requested data has been prefetched; and
to transfer a prefetched memory line to the cache of the first level in response to the stored indication that a memory line associated with an address associated with the requested data has been prefetched. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification