Accessing Memory for Data Decoding

• US 20120030544A1
• Filed: 07/27/2010
• Published: 02/02/2012
• Est. Priority Date: 07/27/2010
• Status: Abandoned Application

• Current Assignee: MediaTek Singapore Pte. Ltd. (MediaTek, Inc.)
• Original Assignee: MediaTek Singapore Pte. Ltd. (MediaTek, Inc.)
• Inventors: Fisher-Jeffes, Timothy Perrin
• Application Number:
  US12/843,894
• Publication Number:
  US 20120030544A1
• Time in Patent Office: Days
• US Class Current: 714/772
• CPC Class Codes: H03M 13/2775 Contention or collision free turbo code internal interleaver
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/395 using a collapsed trellis, e.g. M-step algorithm, radix-n architectures with n>2
• CPC Class Codes: H03M 13/6505 Memory efficient implementations
• CPC Class Codes: H03M 13/6561 Parallelized implementations
• CPC Class Codes: H03M 13/6566 Implementations concerning memory access contentions
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 1/0066 Parallel concatenated codes

Abstract

A method comprises receiving a sequence of unique memory addresses associated with concatenated, convolutionally encoded data elements. The method also comprises identifying each of the unique memory addresses as being included in one group of a plurality of address groups. Each address group substantially includes an equivalent number of unique addresses. The method also comprises, in parallel, accessing at least one memory address associated with each group of the plurality of address groups to operate upon the respective concatenated, convolutionally encoded data elements associated with each of the unique memory addresses being accessed.

Claims

1. A method of accessing a memory for data decoding, comprising:

receiving a sequence of unique memory addresses associated with concatenated, convolutionally encoded data elements;

identifying each of the unique memory addresses as being included in one group of a plurality of address groups, wherein each address group substantially includes an equivalent number of unique addresses; and

in parallel, accessing at least one memory address associated with each group of the plurality of address groups to operate upon the respective concatenated, convolutionally encoded data elements associated with each of the unique memory addresses being accessed.

2. The method of claim 1, wherein operating upon the respective concatenated, convolutionally encoded data elements includes reading the data elements from the unique memory addresses being accessed.

3. The method of claim 1, wherein operating upon the respective concatenated, convolutionally encoded data elements includes writing the data elements to the appropriate unique memory addresses.

4. The method of claim 1, further comprising:

ordering the data elements based upon the address group identifications of the corresponding unique memory addresses.

5. The method of claim 1, wherein the received unique memory addresses associated with the concatenated, convolutionally encoded data elements are interleaved.

6. The method of claim 1, wherein receiving unique memory addresses includes entering one unique memory address into a first buffer and entering another unique memory address into a second buffer.

7. The method of claim 6, wherein the first buffer and second buffer have equivalent lengths.

8. The method of claim 6, wherein the first buffer and the second buffer are configured to store sixteen unique memory addresses.

9. A computing device comprising:

a decoder for receiving a sequence of unique memory addresses associated with concatenated, convolutionally encoded data elements, the decoder is configured to identify each of the unique memory addresses as being included in one group of a plurality of address groups, wherein each address group substantially includes an equivalent number of unique addresses, the decoder is further configured to, in parallel, access at least one memory address associated with each group of the plurality of address groups to operate upon the respective concatenated, convolutionally encoded data elements associated with each of the unique memory addresses being accessed.

10. The computing device of claim 9, wherein to operate upon the respective concatenated, convolutionally encoded data elements, the decoder is configured to read the data elements from the unique memory addresses being accessed.

11. The computing device of claim 9, wherein to operate upon the respective concatenated, convolutionally encoded data elements, the decoder is configured to write the data elements to the appropriate unique memory addresses.

12. The computing device of claim 9, wherein the decoder is further configured to order the data elements based upon the address group identifications of the corresponding unique memory addresses.

13. The computing device of claim 9, wherein the received unique memory addresses associated with the concatenated, convolutionally encoded data elements are interleaved.

14. The computing device of claim 9, wherein the decoder includes a first buffer for entering one unique memory address and a second buffer for entering another unique memory address.

15. The computing device of claim 14, wherein the first buffer and second buffer have equivalent lengths.

16. The computing device of claim 14, wherein the first buffer and the second buffer are configured to store sixteen unique memory addresses.

17. A computer program product tangibly embodied in an information carrier and comprising instructions that when executed by a processor perform a method comprising:

receiving a sequence of unique memory addresses associated with concatenated, convolutionally encoded data elements;

identifying each of the unique memory addresses as being included in one group of a plurality of address groups, wherein each address group substantially includes an equivalent number of unique addresses; and

in parallel, accessing at least one memory address associated with each group of the plurality of address groups to operate upon the respective concatenated, convolutionally encoded data elements associated with each of the unique memory addresses being accessed.

18. The computer program product of claim 17, further comprising instructions that when executed by the processor perform a method comprising:

ordering the data elements based upon the address group identifications of the corresponding unique memory addresses.

19. The computer program product of claim 17, wherein the received unique memory addresses associated with the concatenated, convolutionally encoded data elements are interleaved.

20. The computer program product of claim 17, wherein receiving unique memory addresses includes entering one unique memory address into a first buffer and entering another unique memory address into a second buffer.