SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME

• US 20120032263A1
• Filed: 11/25/2009
• Published: 02/09/2012
• Est. Priority Date: 04/03/2009
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nakazawa, Makoto, Miyamoto, Mitsunobu
• Granted Patent: US 8,420,458 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Abstract

A semiconductor device has a planarizing layer that is made of an inorganic film, and has a recessed portion formed in a region thereof in which a conductive film is disposed. A first contact hole penetrating through at least an interlayer insulating film is formed on a first wiring layer, while a second contact hole penetrating through at least the interlayer insulating film is formed on the conductive film so as to run through the inside of the recessed portion.

Claims

1. A semiconductor device, comprising:

a conductive film formed on an insulating substrate;

a first wiring layer formed on the insulating substrate, having a greater thickness than the conductive film;

a planarizing layer disposed over the insulating substrate so as to cover the first wiring layer and the conductive film; and

an interlayer insulating film disposed on the planarizing layer,

wherein the planarizing layer is made of an inorganic film, and has a recessed portion formed in a region in which the conductive film is disposed,

wherein a first contact hole penetrating through at least the interlayer insulating film and reaching said first wiring layer is formed on the first wiring layer.

wherein a second contact hole penetrating through at least the interlayer insulating film and reaching said conductive film is formed on the conductive film so as to run through an inside of the recessed portion, and

wherein on the interlayer insulating film, a second wiring layer electrically connected to the conductive film through the second contact hole and a third wiring layer electrically connected to the first wiring layer through the first contact hole are formed.

2. The semiconductor device according to claim 1, wherein the conductive film is a semiconductor layer with an impurity element introduced therein.

3. The semiconductor device according to claim 1, wherein an SiNx film that constitutes at least a part of the interlayer insulating film is laminated on a surface of the planarizing layer.

4. The semiconductor device according to claim 1, wherein the planarizing layer is made of SiO₂.

5. The semiconductor device according to claim 1, wherein the planarizing layer is made of SiNx.

6. The semiconductor device according to claim 1, wherein the first wiring layer is a gate electrode of an MOS transistor.

7. A method of manufacturing a semiconductor device, comprising:

forming a conductive film and a first wiring layer that is thicker than said conductive film on an insulating substrate;

forming an inorganic film covering the first wiring layer and the conductive film over the insulating substrate;

forming a photoresist film on a surface of the inorganic film;

exposing the photoresist film to form a resist mask having an opening in a region in which the conductive film is formed;

etching the resist mask and the inorganic film simultaneously to form a recessed portion in a surface of the inorganic film in a region that has been exposed by the opening, and to form a planarizing layer from the inorganic film by planarizing the surface of the inorganic film in a region that has been covered by the resist mask;

forming an interlayer insulating film over the insulating substrate so as to cover the planarizing layer;

forming, on the first wiring layer, a first contact hole penetrating through at least the interlayer insulating film and reaching said first wiring layer;

forming, on the conductive film, a second contact hole penetrating through at least the interlayer insulating film and reaching said conductive film so as to run through an inside of the recessed portion; and

on the interlayer insulating film, a second wiring layer electrically connected to the conductive film through the second contact hole, and a third wiring layer electrically connected to the first wiring layer through the first contact hole.

8. The method of manufacturing a semiconductor device according to claim 7, wherein the conductive film is a semiconductor layer with an impurity element introduced therein.

9. The method of manufacturing a semiconductor device according to claim 7, wherein an SiNx film is laminated on the surface of the planarizing layer in the step of forming the interlayer insulating film.

10. The method of manufacturing a semiconductor device according to claim 7, wherein the planarizing layer is made of SiO₂.

11. The method of manufacturing a semiconductor device according to claim 7, wherein the planarizing layer is made of SiNx.

12. The method of manufacturing a semiconductor device according to claim 7, wherein the first wiring layer is a gate electrode of an MOS transistor.