CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF
First Claim
1. A fabrication method of a chip scale package, comprising the steps of:
- providing a plurality of electronic components, each having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface, and a hard board with a soft layer disposed thereon, and adhering the electronic components to the soft layer via the inactive surfaces thereof;
pressing the electronic components into the soft layer such that the soft layer encapsulates the electronic components while exposing the active surfaces of the electronic components;
forming a dielectric layer on the active surfaces of the electronic components and the soft layer, and forming a plurality of openings in the dielectric layer for exposing the electrode pads, respectively; and
forming a first wiring layer on the dielectric layer and electrically connecting the first wiring layer to the electrode pads.
1 Assignment
0 Petitions
Accused Products
Abstract
A fabrication method of a chip scale package includes providing electronic components, each having an active surface with electrode pads and an opposite inactive surface, and a hard board with a soft layer disposed thereon; adhering the electronic components to the soft layer via the inactive surfaces thereof; pressing the electronic components such that the soft layer encapsulates the electronic components while exposing the active surfaces thereof; forming a dielectric layer on the active surfaces of the electronic components and the soft layer; and forming a first wiring layer on the dielectric layer and electrically connected to the electrode pads, thereby solving the conventional problems caused by directly attaching a chip on an adhesive film, such as film-softening, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the electrode pads and the wiring layer formed in a subsequent RDL process and even waste product.
18 Citations
27 Claims
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1. A fabrication method of a chip scale package, comprising the steps of:
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providing a plurality of electronic components, each having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface, and a hard board with a soft layer disposed thereon, and adhering the electronic components to the soft layer via the inactive surfaces thereof; pressing the electronic components into the soft layer such that the soft layer encapsulates the electronic components while exposing the active surfaces of the electronic components; forming a dielectric layer on the active surfaces of the electronic components and the soft layer, and forming a plurality of openings in the dielectric layer for exposing the electrode pads, respectively; and forming a first wiring layer on the dielectric layer and electrically connecting the first wiring layer to the electrode pads. - View Dependent Claims (2, 3, 6, 7, 8, 10, 11, 13, 14)
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- 4. (canceled)
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9. (canceled)
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12. (canceled)
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15-17. -17. (canceled)
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18. A chip scale package, comprising:
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at least an electronic component having an active surface with a plurality of electrode pads formed thereon and an inactive surface opposite to the active surface; a soft layer encapsulating the electronic component while exposing the active surface of the electronic component; a hard board disposed on a bottom surface of the soft layer; a dielectric layer disposed on the active surface of the electronic component and the soft layer and having a plurality of openings for exposing the electrode pads; and a first wiring layer disposed on the dielectric layer and electrically connected to the electrode pads. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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27-30. -30. (canceled)
Specification