×

CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF

  • US 20120032347A1
  • Filed: 12/17/2010
  • Published: 02/09/2012
  • Est. Priority Date: 08/04/2010
  • Status: Active Grant
First Claim
Patent Images

1. A fabrication method of a chip scale package, comprising the steps of:

  • providing a plurality of electronic components, each having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface, and a hard board with a soft layer disposed thereon, and adhering the electronic components to the soft layer via the inactive surfaces thereof;

    pressing the electronic components into the soft layer such that the soft layer encapsulates the electronic components while exposing the active surfaces of the electronic components;

    forming a dielectric layer on the active surfaces of the electronic components and the soft layer, and forming a plurality of openings in the dielectric layer for exposing the electrode pads, respectively; and

    forming a first wiring layer on the dielectric layer and electrically connecting the first wiring layer to the electrode pads.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×