Shift Register

• US 20120032615A1
• Filed: 12/25/2009
• Published: 02/09/2012
• Est. Priority Date: 05/28/2009
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kikuchi, Tetsuo, Tanaka, Shinya, Yamasaki, Chikao, Shimada, Junya
• Granted Patent: US 8,559,588 B2
• Time in Patent Office: Days
• US Class Current: 315/320
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

Provided is a shift register configured by cascade connecting unit circuits each including a bootstrap circuit. In at least one example embodiment, for the unit circuits, a time period during which a transistor is in an ON state and a clock signal is high level corresponds to a clock passing period. Among transistors whose one conduction terminal is connected to a gate of the transistor, channel lengths of transistors configured such that a low-level potential is fed to gates of the transistors to turn the transistors to an OFF state in the clock passing period and that a low-level potential is applied to the conduction terminal of the transistors in the clock passing period are made longer than the channel length of the transistor. With this, it is possible to reduce a leakage current in the clock passing period, and to prevent the fluctuation of a gate potential of the transistor and dullness in an output signal from occurring.

Claims

1. A shift register comprising:

unit circuits in cascade connection, wherein

each unit circuit includes;

an output transistor provided between a clock terminal and an output terminal, and configured to switch between passing and blocking of a clock signal according to a gate potential; and

one or more control transistors, one conduction terminal of each transistor being connected to a gate of the output transistor,

each unit circuit is configured such that

during a clock passing period in which the output transistor is in an ON state and the clock signal is high level, a gate potential of the output transistor is higher than a high-level potential of the clock signal, and

the control transistors include a transistor whose channel length is longer than that of the output transistor.

2. The shift register according to claim 1, wherein

the control transistors include a transistor configured such that a low-level potential is fed to a gate of the transistor to turn the transistor to an OFF state in the clock passing period and that a low-level potential is applied to the other conduction terminal of the transistor in the clock passing period, and the channel length of the corresponding transistor is longer than that of the output transistor.

3. The shift register according to claim 2, wherein

the control transistors include a transistor configured such that a low-level potential is fed to a gate of the transistor to turn the transistor to an OFF state in the clock passing period and that a low-level potential is fixedly applied to the other conduction terminal of the transistor, and the channel length of the corresponding transistor is longer than that of the output transistor.

4. The shift register according to claim 2, wherein

the control transistors include a transistor configured such that a low-level potential is fed to a gate of the transistor to turn the transistor to an OFF state in the clock passing period and that a signal that becomes low level in the clock passing period is fed to the other conduction terminal of the transistor, and the channel length of the corresponding transistor is longer than that of the output transistor.

5. The shift register according to claim 2, wherein

the control transistors include a plurality of transistors configured such that a low-level potential is fed to a gate of each transistor to turn the transistor to an OFF state in the clock passing period and that a low-level potential is applied to the other conduction terminal of each transistor in the clock passing period, and the channel length of each of the plurality of transistors is longer than that of the output transistor.

6. The shift register according to claim 1, wherein

the control transistors include a transistor whose channel length is longer than that of the output transistor by 0.5 μ

m or more.

7. The shift register according to claim 1, wherein

the gate of the output transistor is capacitively coupled with a conduction terminal of the output transistor on a side of the output terminal.

8. A display device comprising:

a plurality of pixel circuits arranged two-dimensionally; and

a drive circuit including a shift register according to claim 1.

9. A display device comprising:

a plurality of pixel circuits arranged two-dimensionally; and

a drive circuit including a shift register according to claim 2.

10. A display device comprising:

a plurality of pixel circuits arranged two-dimensionally; and

a drive circuit including a shift register according to claim 3.

11. A display device comprising:

a plurality of pixel circuits arranged two-dimensionally; and

a drive circuit including a shift register according to claim 4.

12. A display device comprising:

a plurality of pixel circuits arranged two-dimensionally; and

a drive circuit including a shift register according to claim 5.

13. A display device comprising:

a plurality of pixel circuits arranged two-dimensionally; and

a drive circuit including a shift register according to claim 6.

14. A display device comprising:

a plurality of pixel circuits arranged two-dimensionally; and

a drive circuit including a shift register according to claim 7.