Digital Phase Lock System with Dithering Pulse-Width-Modulation Controller

• US 20120032718A1
• Filed: 08/05/2010
• Published: 02/09/2012
• Est. Priority Date: 08/05/2010
• Status: Active Grant

• Current Assignee: Hong Kong Applied Science And Technology Research Institute Co., Ltd.
• Original Assignee: Hong Kong Applied Science And Technology Research Institute Co., Ltd.
• Inventors: CHAN, Chi Fat, LIN, Chien-Wei, CHUNG, Gordon
• Granted Patent: US 8,248,127 B2
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

A Digital Phase-Locked Loop (DPLL) has a digitally-controlled oscillator (DCO) that generates an output clock frequency determined by a digital input with most-significant-bits (MSB'"'"'s) and a least-significant-bit (LSB). The LSB is generated by a Pulse-Width-Modulation (PWM) controller clocked by a control clock that is the output clock divided by C. A reference clock is compared to a feedback clock that is the output clock divided by M. The PWM controller generates M/C LSB'"'"'s for each reference clock period and loads them in parallel to a parallel-to-serial shift register that serially delivers the LSBs. The pulse width is determined by a fine digital loop filter that filters phase comparison results using a fine time resolution. A coarse digital loop filter generates the MSB'"'"'s from phase comparison results using a coarse time resolution. LSB waveforms are dithered by randomly selecting high-going or low-going pulses and randomly adjusting pulse widths.

Claims

1. A Digital Phase-Locked Loop (DPLL) comprising:

a reference clock input receiving a reference clock having a reference frequency;

a digitally-controlled oscillator (DCO) that generates an output clock having an output frequency that is determined by a digital oscillator input, the digital oscillator input having most-significant-bits (MSBs) and a least-significant-bit (LSB);

a feedback divider that divides the output clock by M to generate a feedback clock, wherein the output frequency is M times the reference frequency when the feedback clock is phase locked to the reference clock, wherein M is a whole number;

a control divider that divides the output clock by C to generate a control clock, wherein the output frequency is C times a control frequency of the control clock, and wherein the control frequency is C/M times the reference frequency when the feedback clock is phase locked to the reference clock, wherein C and M/C are each whole numbers;

a Time-to-Digital Converter (TDC) that receives the reference clock and the feedback clock, the TDC performing phase comparisons of the feedback clock to the reference clock using a coarse time resolution to generate a coarse phase compare signal and using a fine time resolution to generate a fine phase compare signal, wherein the fine time resolution represents a smaller amount of time than the coarse time resolution;

a coarse digital loop filter that receives the coarse time resolution from the TDC and generates the MSBs to the DCO;

a fine digital loop filter that receives the fine time resolution from the TDC and generates a fine loop filter value; and

a Pulse-Width-Modulation (PWM) controller that generates M/C LSB bits for each period of the reference clock, the M/C LSB bits forming a pulse that has a pulse-width determined by the fine loop filter value from the fine digital loop filter, the PWM controller delivering one of the M/C LSB bits to the digital oscillator input of the DCO in response to each period of the control clock,

whereby the PWM controller generates LSB'"'"'s to the digitally-controlled oscillator by modulating the pulse-width in response to the fine loop filter value.

2. The DPLL of claim 1 wherein the PWM controller further comprises:

a parallel-to-serial shift register that is loaded in parallel with the M/C LSB bits for each period of the reference clock, the parallel-to-serial shift register serially delivering the M/C LSB bits to the LSB of the digital oscillator input of the DCO in response to the control clock, wherein a different one of the M/C LSB bits is delivered for each period of the control clock.

3. The DPLL of claim 2 wherein C is 2 or more and M is 10 or more.

4. The DPLL of claim 2 wherein the PWM controller further comprises:

a first random generator that generates a first random number;

a selector that selects as a selected pattern a low-going pattern or a high-going pattern in response to the first random number;

wherein the low-going pattern represents a low-going pulse having the pulse-width;

wherein the high-going pattern represents a high-going pulse having the pulse-width;

wherein the PWM controller generates the M/C LSB bits to represent the selected pattern, whereby low-going and high-going patterns are randomly selected.

5. The DPLL of claim 4 wherein the PWM controller further comprises:

a second random generator that generates a second random number;

a length adjuster that adjusts the pulse-width or a location of the low-going pulse or the high-going pulse within the M/C LSB bits in response to the second random number,

whereby low-going and high-going patterns are randomly adjusted.

6. The DPLL of claim 5 wherein the first random generator is clocked by the reference clock;

wherein the second random generator is clocked by the reference clock;

wherein loading of the parallel-to-serial shift register is synchronized to the reference clock;

wherein unloading of the parallel-to-serial shift register is synchronized to the control clock.

7. The DPLL of claim 2 wherein the PWM controller further comprises:

a first pattern generator that generates a first pattern having a low-going pulse represented by M/C LSB bits in response to the reference clock;

a second pattern generator that generates a second pattern having a high-going pulse represented by M/C LSB bits in response to the reference clock;

a first random generator that generates a first random number in response to the reference clock; and

a mux that receives the first pattern and the second pattern and the first random number, the mux outputting either the first pattern or the second pattern as a selected pattern in response to the first random number,

whereby patterns are randomized by the PWM controller.

8. The DPLL of claim 7 wherein the PWM controller further comprises:

a second random generator that generates a second random number in response to the reference clock;

an adjuster, receiving the selected pattern from the mux, for adjusting a location of the low-going pulse or a locations of the high-going pulse in the selected pattern in response to the second random number,

whereby patterns are randomized by the PWM controller by adjusting the location of the low-going or high-going pulse.

9. The DPLL of claim 8 wherein the DCO produces the output clock with a reduced spur-power phase noise at higher frequencies when the PWM controller randomizes the patterns.

10. A digital phase-locked system comprising:

a digital phase comparator that receives a reference clock and a feedback clock and generates a coarse phase comparison result and a fine phase comparison result;

a coarse digital loop filter that digitally filters the coarse phase comparison result to generate most-significant-bits (MSBs);

a fine digital loop filter that digitally filters the fine phase comparison result to generate a fine filter value;

a Pulse-Width-Modulation (PWM) controller that generates a pattern of least-significant-bits (LSBs) that represent a pulse having a pulse-width determined by the fine filter value;

a parallel-to-serial shift register that is loaded in parallel by the PWM controller with the pattern of LSB'"'"'s;

a digitally-controlled oscillator (DCO) that has a digital input that receives the MSBs and the LSBs and generates an output clock;

a feedback divider that receives the output clock and generates the feedback clock; and

a control divider that receives the output clock and generates a control clock;

wherein the parallel-to-serial shift register shifts the pattern of LSBs to the digital input of the DCO, wherein the pattern of LSBs are serially delivered to the digital input in response to the control clock;

whereby the pulse-width of the pattern of LSBs is modulated in response to the fine filter value.

11. The digital phase-locked system of claim 10 wherein the PWM controller further comprises:

a low-going pattern generator that generates the pattern of LSBs by loading A1 high bits into a first A1 bits of the parallel-to-serial shift register, loading B low bits into a middle B bits of the parallel-to-serial shift register, and loading A2 high bits into a final A2 bits of the parallel-to-serial shift register;

wherein A1+A2 represents the pulse-width determined by the fine filter value for pattern generated by the low-going pattern generator;

a high-going pattern generator that generates the pattern of LSBs by loading B1 low bits into a first B1 bits of the parallel-to-serial shift register, loading A high bits into a middle A bits of the parallel-to-serial shift register, and loading B2 low bits into a final B2 bits of the parallel-to-serial shift register;

wherein A represents the pulse-width determined by the fine filter value for the pattern generated by the high-going pattern generator;

wherein A, B, A1, A2, B1, B2 are whole numbers.

12. The digital phase-locked system of claim 11 wherein the feedback divider divides the output clock by M to generate the feedback clock;

wherein the control divider divides the output clock by C to generate the control clock;

wherein M and C are whole numbers.

13. The digital phase-locked system of claim 12 wherein the PWM controller loads M/C bits into the parallel-to-serial shift register for each period of the reference clock.

14. The digital phase-locked system of claim 13 wherein A1+B+A2 is equal to M/C;

wherein B1+A+B2 is equal to M/C.

15. The digital phase-locked system of claim 11 wherein the PWM controller further comprises:

a random generator that randomly selects the pattern from either the high-going pattern generator or from the low-going pattern generator for loading into the parallel-to-serial shift register,

whereby low-going and high-going patterns are randomly selected to dither the LSBs to the digital input to the DCO.

16. The digital phase-locked system of claim 15 wherein the PWM controller further comprises:

a randomizer that randomly swaps A1 and A2 for the low-going pattern generator, and randomly swaps B1 and B2 for the high-going pattern generator, before loading into the parallel-to-serial shift register,

whereby patterns are randomly swapped to dither the LSBs to the digital input to the DCO.

17. A low-phase-noise Digital Phase-Locked Loop comprising:

a reference clock input receiving a reference clock having a reference frequency;

digitally-controlled oscillator (DCO) means for generating an output clock having an output frequency that is determined by a digital oscillator input, the digital oscillator input having most-significant-bits (MSBs) and a least-significant-bit (LSB);

feedback divider means for dividing the output clock by M to generate a feedback clock, wherein the output frequency is M times the reference frequency when the feedback clock is phase locked to the reference clock, wherein M is a whole number;

control divider means for dividing the output clock by C to generate a control clock, wherein the output frequency is C times a control frequency of the control clock, and wherein the control frequency is C/M times the reference frequency when the feedback clock is phase locked to the reference clock, wherein C and M/C are each whole numbers;

Time-to-Digital Converter (TDC) means, receiving the reference clock and the feedback clock, for coarsely comparing phases of the feedback clock to the reference clock using a coarse time resolution to generate a coarse phase compare signal, and for finely comparing phases of the feedback clock to the reference clock using a fine time resolution to generate a fine phase compare signal, wherein the fine time resolution represents a smaller amount of time than the coarse time resolution;

coarse digital loop filter means for digitally filtering the coarse time resolution from the TDC means to generate the MSBs to the DCO means;

fine digital loop filter means for digitally filtering the fine time resolution from the TDC means to generate a fine loop filter value; and

Pulse-Width-Modulation (PWM) controller means for generating M/C LSB bits for each period of the reference clock, the M/C LSB bits forming a pulse that has a pulse-width determined by the fine loop filter value from the fine digital loop filter means, the PWM controller means also for delivering one of the M/C LSB bits to the digital oscillator input of the DCO means in response to each period of the control clock,

whereby the PWM controller means generates LSB'"'"'s to the DCO means by modulating the pulse-width in response to the fine loop filter value.

18. The low-phase-noise Digital Phase-Locked Loop of claim 17 wherein the PWM controller means further comprises:

parallel-to-serial shift register means, loaded in parallel with the M/C LSB bits for each period of the reference clock, for serially delivering the M/C LSB bits to the LSB of the digital oscillator input of the DCO means in response to the control clock, wherein a different one of the M/C LSB bits is delivered for each period of the control clock.

19. The low-phase-noise Digital Phase-Locked Loop of claim 18 wherein the PWM controller means further comprises:

first random generator means for generating a first random number;

selector means for selecting as a selected pattern a low-going pattern or a high-going pattern in response to the first random number;

wherein the low-going pattern represents a low-going pulse having the pulse-width;

wherein the high-going pattern represents a high-going pulse having the pulse-width;

wherein the PWM controller means generates the M/C LSB bits to represent the selected pattern,

whereby low-going and high-going patterns are randomly selected.

20. The low-phase-noise Digital Phase-Locked Loop of claim 19 wherein the PWM controller means further means comprises:

second random generator means for generating a second random number;

length adjuster means for adjusting a location of the low-going pulse or a location of the high-going pulse within the M/C LSB bits in response to the second random number,

whereby low-going and high-going patterns are randomly adjusted.