SEMICONDUCTOR DEVICE AND DRIVING METHOD OF SEMICONDUCTOR DEVICE

• US 20120033483A1
• Filed: 07/28/2011
• Published: 02/09/2012
• Est. Priority Date: 08/06/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun
• Granted Patent: US 8,531,870 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory cell includes a capacitor, a first transistor, and a second transistor whose off-state current is smaller than that of the first transistor. The first transistor has higher switching speed than the second transistor. The first transistor, the second transistor, and the capacitor are electrically connected in series. Accumulation of charge in the capacitor and release of charge from the capacitor are performed through the first transistor and the second transistor. In this manner, the power consumption of the semiconductor device can be reduced and data can be written and read at higher speed.

Claims

1. A semiconductor device comprising:

a first transistor, wherein a gate of the first transistor is electrically connected to a first wiring;

a second transistor, wherein a gate of the second transistor is electrically connected to a second wiring which is different from the first wiring; and

a capacitor;

wherein one of the first transistor and the second transistor comprises oxide semiconductor,

wherein the first transistor, the second transistor, and the capacitor are electrically connected in series,

2. The semiconductor device according to claim 1, wherein the one of the first transistor and the second transistor comprises a channel formation region in an oxide semiconductor layer.

3. The semiconductor device according to claim 2, the oxide semiconductor layer is provided over the gate of the second transistor.

4. The semiconductor device according to claim 2, wherein the gate of the second transistor is provided over the oxide semiconductor layer.

5. The semiconductor device according to claim 2, wherein a source and a drain of the second transistor are in contact with an upper surface of the oxide semiconductor layer.

6. The semiconductor device according to claim 2, wherein a source and a drain of the second transistor are in contact with a lower surface of the oxide semiconductor layer.

7. The semiconductor device according to claim 1, wherein the other of the first transistor and the second transistor comprises a channel formation region in a semiconductor substrate.

8. The semiconductor device according to claim 1, further comprising an insulating layer provided over the other of the first transistor and the second transistor, wherein the capacitor and the one of the first transistor and the second transistor are provided over the insulating layer.

9. The semiconductor device according to claim 1, wherein the oxide semiconductor comprises indium and zinc.

10. The semiconductor device according to claim 1, wherein the other of the first transistor and the second transistor has higher switching speed than the one of the first transistor and the second transistor.

11. The semiconductor device according to claim 1, wherein one of a source and a drain of the first transistor is electrically connected one of a source and a drain of the second transistor.

12. An electronic device comprising the semiconductor device according to claim 1, wherein the electronic device is one selected from the group consisting of a computer, a mobile phone, a personal digital assistant, a camera, an electronic paper, and a television device.

13. A semiconductor device comprising:

a plurality of memory cells, each of the plurality of memory cells comprising;

a first transistor, wherein a gate of the first transistor is electrically connected to one of a plurality of first word lines;

a second transistor, wherein a gate of the second transistor is electrically connected to one of a plurality of second word lines which is different from the plurality of first word lines; and

a capacitor;

wherein one of the first transistor and the second transistor comprises oxide semiconductor,

wherein the first transistor and the second transistor are electrically connected in series between the capacitor and one of a plurality of bit lines.

14. The semiconductor device according to claim 13, wherein the one of the first transistor and the second transistor comprises a channel formation region in an oxide semiconductor layer.

15. The semiconductor device according to claim 14, the oxide semiconductor layer is provided over the gate of the second transistor.

16. The semiconductor device according to claim 14, wherein the gate of the second transistor is provided over the oxide semiconductor layer.

17. The semiconductor device according to claim 14, wherein a source and a drain of the second transistor are in contact with an upper surface of the oxide semiconductor layer.

18. The semiconductor device according to claim 14, wherein a source and a drain of the second transistor are in contact with a lower surface of the oxide semiconductor layer.

19. The semiconductor device according to claim 13, wherein the other of the first transistor and the second transistor comprises a channel formation region in a semiconductor substrate.

20. The semiconductor device according to claim 13, further comprising an insulating layer provided over the other of the first transistor and the second transistor, wherein the capacitor and the one of the first transistor and the second transistor are provided over the insulating layer.

21. The semiconductor device according to claim 13, wherein the oxide semiconductor comprises indium and zinc.

22. The semiconductor device according to claim 13, wherein the other of the first transistor and the second transistor has higher switching speed than the one of the first transistor and the second transistor.

23. The semiconductor device according to claim 13, wherein one of a source and a drain of the first transistor is electrically connected one of a source and a drain of the second transistor.

24. An electronic device comprising the semiconductor device according to claim 13, wherein the electronic device is one selected from the group consisting of a computer, a mobile phone, a personal digital assistant, a camera, an electronic paper, and a television device.

25. A method for driving a semiconductor device, the semiconductor device comprising:

a first transistor, wherein a gate of the first transistor is electrically connected to a first wiring;

a second transistor, wherein a gate of the second transistor is electrically connected to a second wiring; and

a capacitor;

wherein one of the first transistor the second transistor comprises oxide semiconductor, and

wherein the first transistor, the second transistor, and the capacitor are electrically connected in series,

the method comprising the steps of;

in a first mode, turning off the other of the first transistor and the second transistor to store a charge in the capacitor, and

in a second mode, turning off both of the first transistor and the second transistor to store a charge in the capacitor.

26. The method for driving a semiconductor device according to claim 25, wherein, in the first mode, the one of the first transistor and the second transistor is on when the other of the first transistor and the second transistor is off.

27. A method for driving a semiconductor device, the semiconductor device comprising:

a plurality of memory cells, each of the plurality of memory cells comprising;

a first transistor, wherein a gate of the first transistor is electrically connected to one of a plurality of first word lines;

a second transistor, wherein a gate of the second transistor is electrically connected to one of a plurality of second word lines which is different from the plurality of first word lines; and

a capacitor;

wherein one of the first transistor and the second transistor comprises oxide semiconductor, and

wherein the first transistor and the second transistor are electrically connected in series between the capacitor and one of a plurality of bit lines,

the method comprising the steps of

in a first mode, turning on the one of the first transistor and the second transistor in each of the plurality of memory cells and the other of the first transistor and the second transistor in one of the plurality of memory cells to accumulate a charge in or release a charge from the capacitor in one of the plurality of memory cells in which both of the first transistor and the second transistor are on; and

in a second mode, turning on the first transistor and the second transistor in one of the plurality of memory cells to accumulate a charge in or release a charge from the capacitor in one of the plurality of memory cells in which both of the first transistor and the second transistor are on.