PROGRAMMING OF MEMORY CELLS IN A NONVOLATILE MEMORY USING AN ACTIVE TRANSITION CONTROL
First Claim
1. An integrated circuit comprising:
- a programmable solid-state memory array including a plurality of memory cells arranged in rows and columns, each memory cell including a metal-oxide-semiconductor (MOS) transistor having a gate and a source/drain path;
a plurality of word lines, each coupled to the gate of the MOS transistor in memory cells in an associated row of the memory array;
word line drive circuitry, for energizing the word line associated with a selected row of the memory array;
a plurality of bit lines, each associated with memory cells in an associated column of the memory array;
at least one programming bit line driver for driving programming current to one or more of the plurality of bit lines in a programming operation; and
programming logic, comprising;
switch circuitry, for selectively opening and closing a circuit through which the programming current is conducted via the bit line associated with a selected column of the memory array in the programming operation; and
circuitry, having a first input coupled to the bit line of the selected column and having a second input coupled to receive a reference current, for controlling the switch circuitry responsive to a remainder current, the remainder current corresponding to a portion of the programming current not conducted by a memory cell in the selected column and the selected row.
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Accused Products
Abstract
An electrically programmable non-volatile memory array and associated circuitry, including programming circuitry that adaptively senses completed programming of a selected memory cell. A programming bit line driver is connected to the bit line, and a first transistor has its source/drain path connected in series with the memory cell, and its gate connected to the output of the current comparator. As the MOS transistor in the selected cell becomes programmed, its drain current drawn from the bit line driver decays, and a remainder current into the current comparator increases. Upon the remainder current exceeding the reference current, the comparator turns off the first transistor; a second transistor connected between the source and drain of the cell transistor is turned on. In another approach, a summed current controls the gates of the first and second transistors. Programming terminates, and over-programming is avoided.
45 Citations
34 Claims
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1. An integrated circuit comprising:
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a programmable solid-state memory array including a plurality of memory cells arranged in rows and columns, each memory cell including a metal-oxide-semiconductor (MOS) transistor having a gate and a source/drain path; a plurality of word lines, each coupled to the gate of the MOS transistor in memory cells in an associated row of the memory array; word line drive circuitry, for energizing the word line associated with a selected row of the memory array; a plurality of bit lines, each associated with memory cells in an associated column of the memory array; at least one programming bit line driver for driving programming current to one or more of the plurality of bit lines in a programming operation; and programming logic, comprising; switch circuitry, for selectively opening and closing a circuit through which the programming current is conducted via the bit line associated with a selected column of the memory array in the programming operation; and circuitry, having a first input coupled to the bit line of the selected column and having a second input coupled to receive a reference current, for controlling the switch circuitry responsive to a remainder current, the remainder current corresponding to a portion of the programming current not conducted by a memory cell in the selected column and the selected row. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of programming memory cells in a programmable solid-state memory array including a plurality of memory cells arranged in rows and columns, wherein each memory cell includes a metal-oxide-semiconductor (MOS) transistor comprising a gate and a source/drain path, the method comprising the steps of:
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applying a programming current to the drain of the MOS transistor of a selected memory cell, the source of the MOS transistor of the selected memory cell being coupled to a reference voltage; during the step of applying the programming current, comparing a remainder current from the drain of the MOS transistor of the selected memory cell to a reference current; and responsive to the remainder current exceeding the reference current, turning off a first switch transistor to open a circuit including the source/drain path of the MOS transistor of the selected memory cell in series with the first switch transistor. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A method of programming memory cells in a programmable solid-state memory array including a plurality of memory cells arranged in rows and columns, wherein each memory cell includes a metal-oxide-semiconductor (MOS) transistor comprising a gate and a source/drain path, the method comprising the steps of:
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applying a programming current to the drain of the MOS transistor of a selected memory cell; responsive to the applying step, generating a reference current; during the step of applying the programming current, summing a remainder current from the drain of the MOS transistor of the selected memory cell with the reference current; generating a control voltage responsive to the sum of the remainder and reference currents; and responsive to the control voltage exceeding a threshold voltage, turning off a first switch transistor to open a circuit including the source/drain path of the MOS transistor of the selected memory cell in series with the first switch transistor. - View Dependent Claims (30, 31, 32, 33, 34)
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Specification