DATA WRITING METHOD AND DATA STORAGE DEVICE

• US 20120033492A1
• Filed: 07/27/2011
• Published: 02/09/2012
• Est. Priority Date: 08/04/2010
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Inventors: Chen, Chun-Yi
• Granted Patent: US 8,649,216 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

The invention provides a data writing method. In one embodiment, a data storage device comprises a flash memory. First, the flash memory is directed to read a plurality of programming voltage values for data programming. The programming voltage values are then adjusted to obtain a plurality of adjusted programming voltage values according to difference bits between a plurality of stored data patterns corresponding to the programming voltage values. The adjusted programming voltage values are then sent to the flash memory. The flash memory is then directed to perform data programming according to the adjusted programming voltage values, wherein the data programmed according to the adjusted programming voltage values has a lower error bit rate than that of the data programmed according to the programming voltage values.

Claims

1. A data writing method, wherein a data storage device comprises a flash memory, and the flash memory comprises a plurality of memory cells, comprising:

adjusting a plurality of programming voltage values for programming most significant bits (MSB) of a plurality of stored data patterns of the memory cells of the flash memory to obtain a plurality of adjusted programming voltage values;

receiving a target data from a host; and

directing the flash memory to write the target data thereto according to the adjusted programming voltage values.

2. The data writing method as claimed in claim 1, wherein the programming voltage values respectively correspond to the stored data patterns of the memory cells.

3. The data writing method as claimed in claim 1, wherein adjusting of the programming voltage values comprises:

reading the programming voltage values from a register of the flash memory;

sending the adjusted programming voltage values to the flash memory; and

storing the adjusted programming voltage values in the register.

4. The data writing method as claimed in claim 2, wherein adjusting of the programming voltage values comprises:

determining a plurality of neighboring data pairs comprising the stored data patterns corresponding to the programming voltage values neighboring to each other;

determining a plurality of difference bits between the stored data patterns of the neighboring data pairs;

determining a plurality of target neighboring data pairs with difference bits corresponding to the most significant bits from the neighboring data pairs; and

adjusting the programming voltage values to increase the gaps between the adjusted programming voltage values corresponding to the stored data patterns of the target neighboring data pairs.

5. The data writing method as claimed in claim 1, wherein the flash memory is a triple level cell (TLC) flash memory, and each of the stored data patterns comprise a least significant bit (LSB), a center significant bit (CSB), and a most significant bit (MSB).

6. A data storage device, coupled to a host, comprising:

a flash memory, comprising a plurality of memory cells; and

a controller, adjusting a plurality of programming voltage values for programming most significant bits (MSB) of a plurality of stored data patterns of the memory cells of the flash memory to obtain a plurality of adjusted programming voltage values, receiving a target data from the host, and directing the flash memory to write the target data thereto according to the adjusted programming voltage values.

7. The data storage device as claimed in claim 6, wherein the programming voltage values respectively correspond to the stored data patterns of the memory cells.

8. The data storage device as claimed in claim 6, wherein the controller reads the programming voltage values from a register of the flash memory before the controller adjusts the programming voltage values, and after the controller adjusts the programming voltage values, the controller sends the adjusted programming voltage values to the flash memory, and the flash memory stores the adjusted programming voltage values in the register.

9. The data storage device as claimed in claim 7, wherein when the controller adjusts the programming voltage values, the controller determines a plurality of neighboring data pairs comprising the stored data patterns corresponding to the programming voltage values neighboring to each other, determines a plurality of difference bits between the stored data patterns of the neighboring data pairs, determines a plurality of target neighboring data pairs with the difference bits corresponding to the most significant bits from the neighboring data pairs, and adjusts the programming voltage values to increase the gaps between the adjusted programming voltage values corresponding to the stored data patterns of the target neighboring data pairs.

10. The data storage device as claimed in claim 6, wherein the flash memory is a triple level cell (TLC) flash memory, and each of the stored data patterns comprise a least significant bit (LSB), a center significant bit (CSB), and a most significant bit (MSB).

11. A data writing method, wherein a data storage device comprises a flash memory, comprising:

when the data storage device is enabled, directing the flash memory to read a plurality of programming voltage values for data programming;

adjusting the programming voltage values to obtain a plurality of adjusted programming voltage values according to difference bits between a plurality of stored data patterns corresponding to the programming voltage values;

sending the adjusted programming voltage values to the flash memory; and

directing the flash memory to perform data programming according to the adjusted programming voltage values,

wherein the data programmed according to the adjusted programming voltage values has a lower error bit rate than that of the data programmed according to the programming voltage values.

12. The data writing method as claimed in claim 11, wherein adjusting of the programming voltage values comprises:

determining a plurality of neighboring data pairs from the stored data patterns, wherein the programming voltage values corresponding to the stored data patterns of the neighboring data pairs neighbor to each other;

determining a plurality of difference bits between the stored data patterns of the neighboring data pairs;

selecting a target difference bit with a highest occurrence frequency from the difference bits; and

adjusting the programming voltage values to increase the gaps between the adjusted programming voltage values corresponding to the stored data patterns corresponding to the target difference bit.

13. The data writing method as claimed in claim 12, wherein the target difference bit is the most significant bit, and the adjusted programming voltage values are for programming the most significant bit.

14. The data writing method as claimed in claim 11, wherein adjusting of the programming voltage values comprises:

determining a plurality of neighboring data pairs from the stored data patterns, wherein the programming voltage values corresponding to the stored data patterns of the neighboring data pairs neighbor to each other;

determining a plurality of difference bits between the stored data patterns of the neighboring data pairs;

selecting a target difference bit with a highest error bit rate from the difference bits; and

adjusting the programming voltage values to increase the gaps between the adjusted programming voltage values corresponding to the stored data patterns corresponding to the target difference bit.

15. The data writing method as claimed in claim 14, wherein the target difference bit is the most significant bit, and the adjusted programming voltage values are for programming the most significant bit.

16. The data writing method as claimed in claim 11, wherein the flash memory is a triple level cell (TLC) flash memory, and each of the stored data patterns comprise a least significant bit (LSB), a center significant bit (CSB), and a most significant bit (MSB).

17. The data writing method as claimed in claim 11, wherein the flash memory is a multi level cell (MLC) flash memory, and each of the stored data patterns comprise a least significant bit (LSB and a most significant bit (MSB).

18. A data storage device, comprising:

a flash memory, comprising a plurality of memory cells; and

a controller, when the data storage device is enabled, directing the flash memory to read a plurality of programming voltage values for data programming, adjusting the programming voltage values to obtain a plurality of adjusted programming voltage values according to difference bits between a plurality of stored data patterns corresponding to the programming voltage values, sending the adjusted programming voltage values to the flash memory, and directing the flash memory to perform data programming according to the adjusted programming voltage values,

wherein the data programmed according to the adjusted programming voltage values has a lower error bit rate than that of the data programmed according to the programming voltage values.

19. The data storage device as claimed in claim 18, wherein when the controller adjusts the programming voltage values, the controller determines a plurality of neighboring data pairs from the stored data patterns, determines a plurality of difference bits between the stored data patterns of the neighboring data pairs, selects a target difference bit with a highest occurrence frequency from the difference bits, and adjusts the programming voltage values to increase the gaps between the adjusted programming voltage values corresponding to the stored data patterns corresponding to the target difference bit, wherein the programming voltage values corresponding to the stored data patterns of the neighboring data pairs neighbor to each other.

20. The data storage device as claimed in claim 19, wherein the target difference bit is the most significant bit, and the adjusted programming voltage values are for programming the most significant bit.

21. The data storage device as claimed in claim 18, wherein when the controller adjusts the programming voltage values, the controller determines a plurality of neighboring data pairs from the stored data patterns, determines a plurality of difference bits between the stored data patterns of the neighboring data pairs, selects a target difference bit with a highest error bit rate from the difference bits, and adjusts the programming voltage values to increase the gaps between the adjusted programming voltage values corresponding to the stored data patterns corresponding to the target difference bit, wherein the programming voltage values corresponding to the stored data patterns of the neighboring data pairs neighbor to each other.

22. The data storage device as claimed in claim 21, wherein the target difference bit is the most significant bit, and the adjusted programming voltage values are for programming the most significant bit.

23. The data storage device as claimed in claim 18, wherein the flash memory is a triple level cell (TLC) flash memory, and each of the stored data patterns comprise a least significant bit (LSB), a center significant bit (CSB), and a most significant bit (MSB).

24. The data storage device as claimed in claim 18, wherein the flash memory is a multi level cell (MLC) flash memory, and each of the stored data patterns comprise a least significant bit (LSB) and a most significant bit (MSB).