ADAPTIVE WRITE BIT LINE AND WORD LINE ADJUSTING MECHANISM FOR MEMORY

• US 20120033517A1
• Filed: 08/03/2010
• Published: 02/09/2012
• Est. Priority Date: 08/03/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Hank, Kuo, Ming-Zhang, Chou, Chung-Cheng
• Granted Patent: US 8,331,132 B2
• Time in Patent Office: Days
• US Class Current: 365/203
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A memory includes a capacitor coupled to a write bit line or a word line. An initializer is configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line. An initial level adjuster is configured to adjust a voltage level of a second node at one terminal of the capacitor. A pulse generator configured to supply a pulse to the initial level adjuster to control the initial level adjuster. A boost signal is configured to be supplied to a third node on the other terminal of the capacitor opposite the first node to boost a voltage level of the write bit line lower than ground or to boost a voltage level of the word line higher than a power supply voltage.

Claims

1. A memory, comprising:

a capacitor coupled to a write bit line or a word line;

an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or the word line;

an initial level adjuster configured to adjust a voltage level of a second node at one terminal of the capacitor; and

a pulse generator configured to supply a pulse to the initial level adjuster to control the initial level adjuster;

wherein a boost signal configured to be supplied to a third node on the other terminal of the capacitor opposite the first node to boost a voltage level of the write bit line lower than ground or to boost a voltage level of the word line higher than a power supply voltage.

2. The memory of claim 1, wherein the pulse generator is configured to supply a broader pulse width when coupled to a lower power supply voltage.

3. The memory of claim 1, wherein the initializer is a precharge circuit configured to initialize the voltage level at the first node to the power supply voltage.

4. The memory of claim 1, wherein initializer is configured to initialize the voltage level at the first node to a ground level.

5. The memory of claim 1, wherein the second node and the third node are the same node.

6. The memory of claim 1, wherein the boosted voltage level of the write bit line is lower or the boosted voltage level of the word line is higher when the pulse has a broader pulse width.

7. The memory of claim 1, wherein the pulse generator comprises NAND gate and an odd number of inverters coupled to one input of the NAND gate.

8. The memory of claim 1, wherein the initial level adjuster comprises a transistor and a resistor.

9. A method of biasing a write bit line or a word line for a memory comprising:

adjusting a voltage level on a first node at one terminal of a capacitor using an initial level adjuster, wherein the capacitor is coupled to the write bit line or the word line; and

supplying a boost signal to a second node on one side of the capacitor to boost a voltage level of the write bit line lower than ground or to boost a voltage level of the word line higher than a power supply voltage.

10. The method of claim 9, further comprising initializing a voltage level at a third node between the capacitor and the write bit line or the word line.

11. The method of claim 10, wherein initializing the voltage level comprises precharging the voltage level at the third node to the power supply voltage.

12. The method of claim 10, wherein initializing the voltage level comprises grounding the voltage level at the third node.

13. The method of claim 9, further comprising generating a pulse by a pulse generator coupled to the initial level adjuster.

14. The method of claim 13, further comprising controlling the initial level adjuster with the pulse.

15. The method of claim 13, wherein generating the pulse comprises generating a broader pulse width when the pulse generator is coupled to a lower power supply voltage.

16. The method of claim 13, wherein the pulse generator comprises a NAND gate and an odd number of inverters coupled to one input of the NAND gate.

17. The method of claim 9, wherein the boosted voltage level of the write bit line is lower or the boosted voltage level of the word line is higher when the pulse has a broader pulse width.

18. A memory, comprising:

a capacitor coupled to a write bit line or a word line;

an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line;

an initial level adjuster configured to adjust a voltage level of a second node at one terminal of the capacitor, wherein the initial level adjuster comprises a transistor and a resistor; and

a pulse generator configured to supply a pulse to the initial level adjuster to control the initial level adjuster, the pulse having a broader pulse width when coupled to a lower power supply voltage, wherein the pulse generator comprises a NAND gate and an odd number of inverters coupled to one input of the NAND gate,

wherein a boost signal configured to be supplied to a third node on the other terminal of the capacitor opposite the first node to boost a voltage level of the write bit line lower than ground or boost a voltage level of the word line higher than the power supply voltage.

19. The memory of claim 18, wherein the initializer is a precharge circuit configured to initialize the voltage level between the capacitor and the write bit line or a word line.

20. The memory of claim 18, wherein the boosted voltage level of the write bit line is lower or the boosted voltage level of the word line is higher when the pulse has a broader pulse width.