DECISION FEEDBACK EQUALIZER, RECEIVING CIRCUIT, AND DECISION FEEDBACK EQUALIZATION PROCESSING METHOD
First Claim
1. A decision feedback equalizer comprising:
- L equalization calculation circuits to perform an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample;
a first logic circuit to generate first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on a data decision value for a third sample sampled before sampling the first sample; and
a selection circuit to select one of the first M logical values based on a data decision value for a fourth sample sampled before sampling the third sample, and to output the selected logical value as a data decision value of the first sample.
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Abstract
A decision feedback equalizer includes: L equalization calculation circuits to perform an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample; a first logic circuit to generate first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on a data decision value for a third sample sampled before sampling the first data; and a selection circuit to select one of the first M logical values based on a data decision value for a fourth sample sampled before sampling the third sample, and to output the selected logical value as a data decision value of the first sample.
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Citations
17 Claims
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1. A decision feedback equalizer comprising:
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L equalization calculation circuits to perform an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample; a first logic circuit to generate first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on a data decision value for a third sample sampled before sampling the first sample; and a selection circuit to select one of the first M logical values based on a data decision value for a fourth sample sampled before sampling the third sample, and to output the selected logical value as a data decision value of the first sample. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A receiving circuit comprising:
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a sampling circuit to sample receiving data in synchronization with a sampling clock; a demultiplexing circuit to demultiplex the receiving data sampled by the sampling circuit; a decision feedback equalizer to decide L samples of input data from the demultiplexing circuit; and a phase adjustment circuit to adjust phase of the sampling clock based on the sampled receiving data, wherein the decision feedback equalizer includes, L equalization calculation circuits to perform an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample; a first logic circuit to generate first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on data decision value for a third sample sampled before sampling the first data; and a selection circuit to select one of the first M logical values based on a data decision value for a fourth sample sampled before sampling the third sample, and to output the selected logical value as a data decision value of the first sample. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A decision feedback equalization process method comprising:
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performing an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample by using L equalization calculation circuits; generating first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on a data decision value for a third sample sampled before sampling the first sample by a first logic circuit; selecting one of the M logical values based on a data decision value for a fourth sample sampled before sampling the third sample; and outputting the selected logical value as a data decision value of the first sample. - View Dependent Claims (16, 17)
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Specification