METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

• US 20120034747A1
• Filed: 10/20/2011
• Published: 02/09/2012
• Est. Priority Date: 10/02/2009
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Chun-Hsien
• Granted Patent: US 8,288,262 B2
• Time in Patent Office: Days
• US Class Current: 438/300
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A method for fabricating a semiconductor device is described. A polysilicon layer is formed on a substrate. The polysilicon layer is doped with an N-type dopant. A portion of the polysilicon layer is then removed to form a plurality of dummy patterns. Each dummy pattern has a top, a bottom, and a neck arranged between the top and the bottom, where the width of the neck is narrower than that of the top. A dielectric layer is formed on the substrate to cover the substrate disposed between adjacent dummy patterns, and the top of each dummy pattern is exposed. Thereafter, the dummy patterns are removed to form a plurality of trenches in the dielectric layer. A plurality of gate structures is formed in the trenches, respectively.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a polysilicon layer on a substrate;

doping an N-type dopant into the polysilicon layer;

removing a portion of the polysilicon layer to form a plurality of dummy patterns, each of the plurality of dummy patterns having a top, a bottom, and a neck arranged between the top and the bottom, wherein a width of the neck is narrower than a width of the top;

forming a dielectric layer on the substrate, the dielectric layer covering the substrate disposed between two adjacent dummy patterns and exposing the top of each dummy pattern;

removing the plurality of dummy patterns to form a plurality of trenches in the dielectric layer; and

forming a plurality of gate structures in the trenches respectively.

2. The method of fabricating the semiconductor device as claimed in claim 1, wherein a depth of the polysilicon layer doped with a highest concentration of the N-type dopant and the neck are substantially located on the same horizontal level of height.

3. The method of fabricating the semiconductor device as claimed in claim 1, wherein a concentration of the N-type dopant doped in a bottom of the polysilicon layer is greater than a concentration of the N-type dopant doped in a top of the polysilicon layer.

4. The method of fabricating the semiconductor device as claimed in claim 1, wherein a concentration of the N-type dopant doped increases gradually from a top to a bottom of the polysilicon layer.

5. The method of fabricating the semiconductor device as claimed in claim 1, further comprising doping another N-type dopant into the polysilicon layer.

6. The method of fabricating the semiconductor device as claimed in claim 1, wherein the N-type dopant is phosphorus (P), antimony (Sb), or arsenic (As).

7. The method of fabricating the semiconductor device as claimed in claim 1, wherein when the N-type dopant is phosphorus, an energy for doping is within a range of 1 Kev to 20 KeV and a dose for doping is within a range of 1E15 cm⁻

2 to 8E15 cm<sup>−

2</sup>.

8. The method of fabricating the semiconductor device as claimed in claim 1, wherein the top and the neck have a first height therebetween, the neck and the bottom have a second height therebetween, and a ratio of the first height to the second height is substantially 2:

1.

9. The method of fabricating the semiconductor device as claimed in claim 1, wherein an included angle between a sidewall of a top of each of the plurality of trenches and a surface of the dielectric layer is larger than 90°

.

10. The method of fabricating the semiconductor device as claimed in claim 1, wherein the step of removing a portion of the polysilicon layer comprises performing an etching process using a halogen-containing reactant.

11. The method of fabricating the semiconductor device as claimed in claim 1, before removing the plurality of dummy patterns, further comprising forming a high dielectric constant layer between the substrate and each of the plurality of dummy patterns.

12. The method of fabricating the semiconductor device as claimed in claim 1, further comprising forming a source/drain region in the substrate at respective sides of the gate structure.

13. The method of fabricating the semiconductor device as claimed in claim 12, wherein the step of forming the source/drain region comprises performing an ion implantation process or a selective epitaxy growth process.

14. The method of fabricating the semiconductor device as claimed in claim 1, after forming the plurality of dummy patterns and before forming the dielectric layer, further comprising forming a spacer on a sidewall of each of the plurality of dummy patterns.