INTERCONNECT THAT ELIMINATES ROUTING CONGESTION AND MANAGES SIMULTANEOUS TRANSACTIONS

• US 20120036296A1
• Filed: 10/18/2011
• Published: 02/09/2012
• Est. Priority Date: 06/25/2007
• Status: Abandoned Application

• Current Assignee: META Platforms Technologies LLC (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Original Assignee: Sonics Incorporated (Meta Platforms, Inc. (f/k/a Facebook, Inc.))
• Inventors: Wingard, Drew E., Chou, Chien-Chun, Hamilton, Stephen W., Swarbrick, Ian Andrew, Vakilotojar, Vida
• Application Number:
  US13/276,041
• Publication Number:
  US 20120036296A1
• Time in Patent Office: Days
• US Class Current: 710/105
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect. The flow control logic for the interconnect applies a flow control splitting protocol to permit transactions from each initiator thread and/or each initiator tag stream to be outstanding to multiple channels in a single aggregate target at once, and therefore to multiple individual targets within an aggregate target at once. The combined flow control logic and flow control protocol allows the interconnect to manage simultaneous requests to multiple channels in an aggregate target from the same thread or tag at the same time.

Claims

1. An integrated circuit having multiple initiator IP cores and multiple target IP cores that communicate request transactions over an interconnect, where the interconnect provides a shared communications bus between the multiple initiator IP cores and multiple target IP cores, comprising:

flow control logic for the interconnect is configured to apply a flow control splitting protocol to permit transactions from a first initiator thread or a first initiator tag stream to be outstanding to multiple channels in a single aggregate target at once, and therefore to multiple individual target IP cores within the aggregate target at once, where the combination of the flow control logic and the flow control splitting protocol allows the interconnect to manage simultaneous requests to multiple channels in the aggregate target from the same first initiator thread or the first initiator tag at the same time.

2. The integrated circuit of claim 1, where the flow control logic also includes merger and thread splitter units in its architecture to intentionally split request transactions in an initiator agent, or as early as possible along the path in the interconnect to target agents for the multiple channels of the aggregate target, and this approach avoids creating a centralized point that could act as a bandwidth choke point and routing congestion point.

3. The integrated circuit of claim 1, where a distribution of the flow control logic eliminates a need to have all the communication paths in the interconnect pass through a single choke point because many distributed pathways exist in this shared communications bus, and the flow control logic for the interconnect is configured to apply a flow control splitting protocol to also split the request transactions early where it makes sense due to a physical routing of parts of that set of request transactions being routed on separate physical pathways in the interconnect as well as being routed to target IP cores physically located in different areas on the integrated circuit, and

where flow control splitting protocol is also configured to allow multiple transactions to be issued and serviced in parallel, which increases an efficiency of each initiator in being able to start having more transactions serviced in the same period of time, where a first and a second transaction from a first initiator IP core are issued prior to the first transaction being completely serviced by a first target IP core resulting in that the first initiator IP core and the first target IP core are working on multiple transactions at the same time.

4. The integrated circuit of claim 1, where the interconnect has multiple thread merger and thread splitter units in the flow control logic distributed over the interconnect that maintain request order for read and write request transactions over the interconnect, where the one or more thread splitter units route request transactions from a first initiator IP core generating a set of request transactions in the first initiator thread down two or more different physical paths to the target IP cores physically located in different areas on the integrated circuit.

5. The integrated circuit of claim 1, where the interconnect implements an address map with assigned address for the target IP cores in the integrated circuit to route request transactions between the target IP cores and the initiator IP cores in the integrated circuit, where the interconnect is configured to interrogate the address map based on a logical destination address associated with a first request to the aggregate target with two or more interleaved memory channels, and determines which memory channels will service the first request and how to route the first request to the physical IP addresses of each memory channel in the aggregate target servicing that request so that an initiator IP core need not know of the physical IP addresses of each memory channel in the aggregate target, and

where flow control splitting protocol implemented in the flow control logic is also configured to also allow multiple transactions from either 1) the same initiator IP core thread or 2) the same initiator IP core set of tags to be outstanding to the multiple channels of the aggregated target at the same time, and

the multiple channels in the aggregated target map to target IP cores having physically different addresses.

6. The integrated circuit of claim 1, where the flow control logic in the interconnect maintains a request order within the first initiator thread and an expected response order to those requests, and where the interconnect includes three or more initiator agents and three or more target agents, where two or more target agents are located at physically different locations coupling to the interconnect but belong to the same aggregate target with multiple channels.

7. The integrated circuit of claim 1, where one or more thread splitter units with the flow control logic in a request network splits the path links to the aggregate target with multiple channels, which is a Dynamic Random-Access Memory (DRAM) IP core, where a first request travels a first link to a first channel in the multi-channel target DRAM and a second request travels a second link to a second channel in the multi-channel target DRAM and two or more target agents are coupled to the multi-channel target DRAM, and a first target agent is assigned to the first channel and a second target agent is assigned to the second channel for the multi-channel target DRAM, where the first and second target agents are at physically different locations coupling to the interconnect and belong to the same aggregate target with multiple channels, and where the thread splitter units and other associated flow control logic minimize the transaction and routing congestion issues associated with a centralized channel splitter.

8. The integrated circuit of claim 1, where a distributed implementation in each thread splitter unit and thread merger unit in the flow control logic is configured to allow them to interrogate a local system address map to determine both 1) thread routing and 2) thread buffering until a switch of physical paths can occur, and where the thread splitter units and thread merger units cooperate end-to-end to ensure ordering without a need to install one or more full transaction reorder buffers within the interconnect.

9. The integrated circuit of claim 1, where the flow control logic internal to 1) the interconnect or 2) in the initiator agent interrogates the address map and a known structural organization of the aggregated target in the integrated circuit to decode an interleaved address space of the aggregated target to determine any physical distinctions between the target IP cores making up the aggregated target IP core in order to determine which targets making up the aggregated target need to service a given request from an initiator IP core, and where the flow control logic applies a flow control splitting protocol to allow multiple transactions from the same thread to be outstanding to multiple channels of the aggregated target at any given time and the multiple channels in the aggregated target map to target IP memory cores having physically different addresses.

10. The integrated circuit of claim 1, where an initiator agent interfacing the interconnect for a first initiator IP core interrogates an address map based on a logical destination address associated with a request to the aggregate target that has interleaved two or more memory channels, and determines which memory channels will service the request and how to route the request to the physical IP addresses of each memory channel in the aggregate target servicing that request so that any initiator IP core need not know of the physical IP addresses of each memory channel in the aggregate target.

11. The integrated circuit of claim 1, where the flow control logic is configured to apply a flow control splitting protocol to allow multiple transactions from the same thread to be outstanding to the multiple channels of the aggregated target at any given time and the multiple channels in the aggregated target map to target memory cores having physically different addresses.

12. The integrated circuit of claim 1, where chopping logic and the flow control logic cooperate to allow requests that are part of a request burst transaction to cross an interleave boundary of the aggregate target such that some request transfers are sent to one channel target while others are sent to another channel target within the aggregate target, where the chopping logic is internal to the interconnect and is configured to chop individual burst transactions that cross channel boundaries headed for channels in the aggregate target into two or more requests.

13. The integrated circuit of claim 1, where the initiator cores do not need a priori knowledge of a memory'"'"'s address structure and organization in the aggregate target, rather one or more initiator agents have this structural and organizational knowledge of memory channels to choose a true address of the target of a request transaction, a route to the target of the request transaction from a first initiator IP core across the interconnect, and then a channel within the aggregated target.

14. The integrated circuit of claim 1, where address decoding of an intended address of the request transaction from the first initiator thread happens as soon as the request transaction enters an interface of the interconnect, and the flow control logic interrogates an address map and a known structural organization of each aggregated target IP core in the integrated circuit to decode an interleaved address space of the aggregated targets to determine the physical distinctions between the target IP cores making up a particular aggregated target IP core in order to determine which target IP cores making up a first aggregated target needs to service a current request transaction.

15. The integrated circuit of claim 1, where two or more thread splitter units with the flow control logic are configured to route request transactions from an initiator IP core generating a set of transactions in the first initiator thread down two or more different physical paths in the interconnect by routing a first request with a destination address headed to a first physical location on the integrated circuit, which is a first target, and other requests within that first initiator thread having a destination address headed to different physical locations on the integrated circuit from the first physical location, where the first physical location is a first channel and the different physical location is a second channel making up part of the aggregate target, where the first and second channels share an address region to appear as single logical aggregated target, and where a channel merger component in a response path maintains response path ordering, where a mechanism to re-order responses in the response path includes passing information from a channel splitter in the request path to a corresponding channel merger component in the response path, and the information passed over tells the thread merger component which incoming thread the next response burst transaction should come from.

16. The integrated circuit of claim 1, where a request path in the interconnect includes a series of splitter and merger units in the flow control logic distributed across the interconnect to create different physical paths across the interconnect to the aggregate target with multiple channels, and where the aggregate target with multiple channels has two or more discreet memories channels including on-chip IP cores and off-chip memory cores that are interleaved with each other to appear to system software and other IP cores as a single memory in a system address space.

17. The integrated circuit of claim 1, where the interconnect implements the flow control logic and flow control protocol internal to the interconnect itself to manage expected execution ordering of a set of issued requests within the same first initiator thread that are serviced and responses returned in order with respect to each other but independent of an ordering of another thread, and the flow control logic at a thread splitter unit permits transactions from one initiator thread to be outstanding to multiple channels at once and therefore to multiple individual target IP cores within a multi-channel target at once, where different channels are mapped to two individual target IP cores within the aggregate target with multiple channels, and

the integrated circuit has chopping logic to chop individual burst requests that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more burst requests from the same thread, where the chopping logic cooperates with a detector to detect when the starting address of an initial word of requested bytes in the burst request and ending address of the last word of requested bytes in the burst request causes the requested bytes in that burst request to span across one or more channel address boundaries to fulfill all of the word requests in the burst request transaction.

18. A method of communicating requests over an interconnect in an integrated circuit having multiple initiator IP cores and multiple target IP cores, where the interconnect provides a shared communications bus between the multiple initiator IP cores and multiple target IP cores, comprising:

applying a flow control splitting protocol to permit transactions from one initiator thread or one initiator tag stream to be outstanding to multiple channels in a single aggregate target at once, and therefore to multiple individual target IP cores within the aggregate target at once, where the combined flow control logic and flow control protocol allows the interconnect to manage simultaneous requests to multiple channels in the aggregate target from a same thread or tag at the same time.