MONOLITHIC MICROWAVE INTEGRATED CIRCUIT

• US 20120037969A1
• Filed: 08/12/2010
• Published: 02/16/2012
• Est. Priority Date: 08/12/2010
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Sanders, Paul W., Burger, Wayne R., Dao, Thuy B., Keys, Joel E., Petras, Michael F., Pryor, Robert A., Ren, Xiaowei
• Granted Patent: US 9,064,712 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2223/6683 for monolithic microwave integrated circuit [MMIC]
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 27/0617 comprising components of the field-effect type H01L27/0251 takes precedence
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/40 : Capacitors
• CPC Class Codes: H01L 29/7816 : Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H03F 3/195 : in integrated circuits

Abstract

Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44′, 45′) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1′, 52-1′, 94, 94′, 94″) overlying the substrate (60). The active transistor(s) (41′) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42′, 43′) are also formed over the front face (63) of the substrate (60). Various terminals (42-1′, 42-2′, 43-1, 43-2′,50′, 51′, 52′, 42-1′, 42-2′, etc.) of the transistor(s) (41′), capacitor(s) (42′, 43′) and inductor(s) (44′, 45′) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98′) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (44′, 45′) and heavy current carrying conductors (52-1′) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC (46, 58) previously unobtainable.

Claims

1. A monolithic microwave integrated circuit, comprising:

a semiconductor substrate having a bulk resistivity equal or greater than about 100 Ohm-cm, and having a front surface and a rear surface;

at least one transistor in the semiconductor substrate and having an input terminal, an output terminal and a reference terminal;

at least one capacitor monolithically formed over the semiconductor substrate;

at least one inductor monolithically formed over the semiconductor substrate; and

planar interconnections overlying the semiconductor substrate coupling the at least one transistor, capacitor, and inductor to form the monolithic integrated circuit.

2. The monolithic microwave integrated circuit of claim 1, further comprising an input node thereof and an output node thereof, both supported by the front surface of the semiconductor substrate, and a reference node thereof supported by the rear surface of the semiconductor substrate.

3. The monolithic microwave integrated circuit of claim 2, further comprising multiple conductive through-substrate vias coupling one or more of the at least one transistor, the at least one capacitor and the at least one inductor to the reference node.

4. The monolithic microwave integrated circuit of claim 3, wherein a first of the multiple conductive through-substrate vias couples the reference terminal of the at least one transistor to the reference node.

5. The monolithic microwave integrated circuit of claim 3, wherein a second of the multiple through-substrate vias couples a first terminal of the at least one capacitor to the reference node.

6. The monolithic microwave integrated circuit of claim 1, wherein the at least one transistor is a lateral transistor.

7. The monolithic microwave integrated circuit of claim 1, wherein the at least one capacitor is a planar capacitor, and wherein the at least one inductor is a planar inductor.

8. The monolithic microwave integrated circuit of claim 2, wherein the semiconductor substrate further comprises:

multiple conductive through-substrate vias each having a terminal coupled to the reference node;

two monolithic capacitors formed over the front surface of the semiconductor substrate, each having first and second terminals;

two monolithic inductors formed over the front surface of the semiconductor substrate, each having first and second terminals;

wherein the first terminal of the first capacitor is coupled to the first terminal of the first inductor and the second terminal of the first capacitor is coupled to a first of the multiple through substrate vias, and the second terminal of the first inductor is coupled to the input terminal of the transistor;

wherein the second capacitor and second inductor are serially coupled to form a combination, the combination having first and second terminals; and

wherein the first terminal of the combination is coupled to the output terminal of the at least one transistor and the second terminal of the combination is coupled to a second of the multiple conductive through-substrate vias.

9. The monolithic microwave integrated circuit of claim 1, wherein the at least one inductor comprises a high conductivity metal 0.1-10 micrometers thick.

10. A method for forming a monolithic microwave integrated circuit having an input terminal, an output terminal and a reference terminal, the method comprising:

providing a high resistivity initial semiconductor substrate having an initial thickness between a first surface and an initial second surface;

forming at least one transistor in the initial semiconductor substrate with input terminal, output terminal and reference terminal proximate the first surface;

forming one or more conductor filled substrate vias extending into the initial semiconductor substrate through the first surface;

forming one or more planar capacitors over the first surface of the initial substrate, each capacitor having first and second terminals;

forming one or more planar inductors over the first surface of the initial substrate, wherein the first terminal or the second terminal of the one or more planar capacitors is coupled to a first terminal or a second terminal of the one or more planar inductors wherein other terminals of the one or more planar inductors are coupled to through substrate vias, to one or more terminals of the transistor or to one or more terminals of the microwave integrated circuit;

reducing the initial thickness, thereby creating a new rear surface of a thinned substrate on which inner ends of the substrate vias are exposed; and

applying a conductor to the new rear surface of the thinned substrate so that the exposed inner ends of the substrate vias are electrically connected to the conductor.

11. The method of claim 10, wherein:

the step of forming one or more planar capacitors comprises, forming first and second planar capacitors over the first surface of the initial substrate, each capacitor having first and second terminals; and

the step of forming one or more planar inductors comprises, forming first and second planar inductors over the first surface, each inductor having first and second terminals; and

wherein the first terminal of the first capacitor is coupled to the first terminal of the first inductor and the second terminal of the first inductor is coupled to the transistor input; and

wherein the first terminal of the second capacitor is coupled to the transistor output and the second terminal of the second capacitor is coupled to the first terminal of the second inductor; and

wherein the second terminal of the first capacitor, the second terminal of the second inductor and the reference terminal of the transistor are coupled to at least one of the conductor filled substrate vias.

12. The method of claim 10, wherein the initial substrate has a resistivity equal or greater than about 100 Ohm-cm.

13. The method of claim 12, wherein the initial substrate has a resistivity equal or greater than about 500 Ohm-cm.

14. The method of claim 12, wherein the initial substrate has a resistivity equal or greater than about 1000 Ohm-cm.

15. The method of claim 10, wherein the step of forming one or more planar inductors comprises, forming the inductors using copper, gold, silver or a combination thereof.

16. The method of claim 14, wherein the copper, gold, silver or combination thereof is at least about 3 micrometers thick.

17. A monolithic microwave integrated circuit having a circuit input terminal, a circuit output terminal and a circuit reference terminal, comprising:

a semiconductor substrate having a bulk resistivity equal or greater than about 100 Ohm-cm, and having a front surface and a rear surface, wherein the rear surface has thereon the circuit reference terminal;

at least one LDMOS transistor formed in the substrate and having a transistor input terminal, a transistor output terminal and a transistor reference terminal, wherein the transistor reference terminal is coupled to the circuit reference terminal;

at least first and second monolithic planar capacitors overlying the front surface;

at least first and second monolithic planar inductors overlying the front surface; and

wherein the first capacitor is coupled between the circuit input terminal and the circuit reference terminal, and the first inductor is coupled between the circuit input terminal and the transistor input terminal; and

wherein the second capacitor and the second inductor are coupled in series to from a combination, and a first terminal of the combination is coupled to the transistor output terminal and to the circuit output terminal and a second terminal of the combination is coupled to the circuit reference terminal.

18. The circuit of claim 17, wherein the substrate substantially comprises float zone silicon.

19. The circuit of claim 17, wherein at least one of the first and second inductors is formed from substantially high purity copper.

20. The circuit of claim 19, wherein the high purity copper has a thickness of at least about 0.5 micrometers.