Power Semiconductor Chip with a Formed Patterned Thick Metallization Atop

• US 20120037981A1
• Filed: 10/21/2011
• Published: 02/16/2012
• Est. Priority Date: 01/20/2009
• Status: Active Grant

• Current Assignee: Il Kwan Lee
• Original Assignee: Il Kwan Lee
• Inventors: Lee, Il Kwan
• Granted Patent: US 8,354,334 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48724 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48824 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK1+TK2; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

Claims

1. A power semiconductor chip comprising:

an active area having a plurality of trenches filed with an insulated gate material extending into an epitaxial layer overlaying a substrate layer functioning as a drain;

body regions extending between trenches;

source regions disposed in body regions next to the trenches;

a dielectric layer overlaying the semiconductor surface with contact openings thereon; and

a metal layer overlaying the dielectric layer contacting the source regions through the contact openings, wherein said metal layer comprising a thin metallization layer in the bottom and a thick metallization layer on the top with the composition of said thin metallization layer comprises a Si content higher than the Si content of said thick metallization layer.

2. The power semiconductor chip of claim 1 wherein said thick metallization layer is free of Si.

3. The power semiconductor chip of claim 1 wherein said thin metallization layer has a thickness between 0.5 micron and 1 micron.

4. The power semiconductor chip of claim 1 wherein said metal layer has a combined thickness of 4-5 micron for Cu wire bonding.

5. The power semiconductor chip of claim 1 wherein the ratio of thick metallization thickness to thin metallization thickness ranges from about 3:

1 to about 7;

1.

6. The power semiconductor chip of claim 1 wherein said metal layer has a top surface of step profile substantially conforming to the topography of its underlying dielectric layer.

7. The power semiconductor chip of claim 1 further comprising:

a termination area having a gate contact opening opened through the dielectric layer on top of a gate runner trench for providing metal contact to the insulated gate.

8. The power semiconductor chip of claim 7 further comprising:

a metal layer overlaying the dielectric layer contacting the insulated gate through the contact openings, and said metal layer further comprising a thin metallization layer at the bottom and a thick metallization layer on the top.

9. A power semiconductor chip comprising:

a power semiconductor chip with a plurality of contact zones;

a dielectric layer overlaying the semiconductor surface extending over said plurality of contact zones and having a plurality of contact openings thereon;

a metal layer overlaying the dielectric layer contacting the source regions through the contact openings, wherein said metal layer comprising a thin metallization layer in the bottom and a thick metallization layer on the top with a composition of said thin metallization layer different from a composition of said thick metallization layer, wherein the ratio of thick metallization thickness to thin metallization thickness ranges from about 3;

1 to about 7;

1.

10. The power semiconductor chip of claim 9 wherein said thin metallization layer comprises 0.5˜

1.5% of Si.

11. The power semiconductor chip of claim 9 wherein said thin metallization layer has a thickness between 0.5 micron and 1 micron.

12. The power semiconductor chip of claim 9 wherein said metal layer has a combined thickness of 4 to 5 micron for Cu wire bonding.

13. The power semiconductor chip of claim 9 wherein said metal layer has a top surface of step profile substantially conforming to the topography of its underlying dielectric layer.

14. The power semiconductor chip of claim 9 further comprising:

a termination area having a gate contact opening opened through the dielectric layer on top of a gate runner trench for providing metal contact to insulated gate.

15. The power semiconductor chip of claim 14 further comprising:

a metal layer overlaying the dielectric layer contacting the insulated gate through the contact openings, and said metal layer further comprising a thin metallization layer at the bottom and a thick metallization layer on the top.