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Power Semiconductor Chip with a Formed Patterned Thick Metallization Atop

  • US 20120037981A1
  • Filed: 10/21/2011
  • Published: 02/16/2012
  • Est. Priority Date: 01/20/2009
  • Status: Active Grant
First Claim
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1. A power semiconductor chip comprising:

  • an active area having a plurality of trenches filed with an insulated gate material extending into an epitaxial layer overlaying a substrate layer functioning as a drain;

    body regions extending between trenches;

    source regions disposed in body regions next to the trenches;

    a dielectric layer overlaying the semiconductor surface with contact openings thereon; and

    a metal layer overlaying the dielectric layer contacting the source regions through the contact openings, wherein said metal layer comprising a thin metallization layer in the bottom and a thick metallization layer on the top with the composition of said thin metallization layer comprises a Si content higher than the Si content of said thick metallization layer.

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