Trench mosfet with integrated schottky rectifier in same cell

• US 20120037983A1
• Filed: 08/10/2010
• Published: 02/16/2012
• Est. Priority Date: 08/10/2010
• Status: Abandoned Application

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: Hshieh, Fwu-Iuan
• Application Number:
  US12/805,611
• Publication Number:
  US 20120037983A1
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor power device comprising a plurality of trench MOSFETs integrated with Schottky rectifier in same cell is disclosed. The invented semiconductor power device comprises a tilt-angle implanted drift region having higher doping concentration than epitaxial layer to reduce Vf in Schottky rectifier portion and to reduce Rds in trench MOSFET portion while maintaining a higher breakdown voltage by implementation of thick gate oxide in trench bottom of trenched gates. Furthermore, the invented semiconductor power device further comprises a Schottky barrier height enhancement region to enhance the barrier layer covered in trench bottom of trenched source-body-Schottky contact in Schottky rectifier portion.

Claims

1. A semiconductor power device comprising a plurality of trenched gates surrounded by source regions of a first conductivity type encompassed in body regions of a second conductivity type opposite to said first conductivity type in active area, said semiconductor power device further comprising:

a substrate of said first conductivity type;

an epitaxial layer of said first conductivity type encompassing said body regions and said source regions supported on said substrate, having a lower doping concentration than said substrate;

said trenched gates formed within said epitaxial layer further having a first gate oxide layer in lower portion of said trenched gates and having a second gate oxide layer in upper portion of said trenched gates, wherein said first gate oxide layer is thicker than said second gate oxide layer;

a plurality of tilt-angle implanted drift regions of said first conductivity type formed in mesa area between every two adjacent said trenched gates encompassed in said epitaxial layer below said body region and having a higher doping concentration than said epitaxial layer;

a plurality of trenched source-body-Schottky contacts penetrating through an insulation layer covering top surface of said epitaxial layer, further extending through said source regions and said body regions and into said tilt-angle implanted drift regions in said active area wherein trench bottom and lower portion trench sidewalls of said trenched source-body-Schottky contacts below said body regions covered with a Schottky barrier layer to function as an integrated Schottky rectifier;

a plurality of ohmic contact doped regions of said second conductivity type surrounding sidewalls of said trenched source-body-Schottky contacts below said source regions, above said integrated Schottky rectifier, and having a higher doping concentration than said body regions.

2. The semiconductor power device of claim 1 further comprising a Schottky barrier height enhancement region of said first conductivity type surrounding said integrated Schottky rectifier disposed on sidewall and bottom of each said trenched source-body-Schottky contact below said ohmic contact doped region, said Schottky barrier height enhancement region has a lower doping concentration than said epitaxial layer.

3. The semiconductor power device of claim 1, wherein each of said trenched gates comprising a bottom shielded gate segment padded by said first gate oxide layer on sidewall of a lower portion of said trenched gate and a top gate segment padded by said second gate oxide layer on sidewall at an upper portion of said trenched gate, wherein said bottom shielded gate segment is insulated from said top gate segment by said second gate oxide layer.

4. The semiconductor power device of claim 3, wherein said bottom shielded gate segment and said top gate segment further comprising doped poly-silicon layer.

5. The semiconductor power device of claim 3, wherein said bottom shielded gate segment is connected to a source metal and said top gate segment connected to a gate metal.

6. The semiconductor power device of claim 1, wherein each of said trenched gates comprising a single gate segment padded by said first gate oxide layer on sidewall of a lower portion of said trenched gate and said second gate oxide layer on sidewall at an upper portion of said trenched gate.

7. The semiconductor power device of claim 6, wherein said single gate segment further comprising doped poly-silicon layer connected to a gate metal.

8. The semiconductor power device of claim 1, wherein said ohmic contact doped regions are formed within said body regions.

9. The semiconductor power device of claim 1, wherein said ohmic contact doped regions are formed extended below said body regions for avalanche enhancement.

10. The semiconductor power device of claim 1, wherein said semiconductor power device further comprising trenched metal oxide semiconductor field effect transistor.

11. The semiconductor power device of claim 1, wherein said trenched source-body-Schottky contacts are filled with tungsten plugs padded by a barrier layer Ti/TiN, Co/TiN or Ta/TiN.

12. The semiconductor power device of claim 11 further comprising a source metal covering top surface of said insulation layer and said tungsten plugs filled in said trenched source-body-Schottky contacts.

13. The semiconductor power device of claim 1, wherein said insulation layer further comprising a BPSG layer and an NSG layer beneath.

14. The semiconductor power device of claim 13, wherein said trenched source-body-Schottky contacts have greater width within said BPSG layer than within other portions.

15. The semiconductor power device of claim 1 further comprising a termination area next to said active area, said termination area further having a plurality of trenched gates penetrating through said body regions and said tilt-angle implanted drift regions and into said epitaxial layer, wherein said trenched gates in said termination area are same as those in active area.

16. The semiconductor power device of claim 1, wherein said Schottky barrier layer is Ti silicide, Co silicide or Ta silicide.

17. The semiconductor power device of claim 12, wherein said source metal is Ti/Al alloys, Ti/Ni/Ag or Cu.

18. The semiconductor power device of claim 1, wherein said tilt-angle implanted drift regions have lower doping concentration at middle of said mesa area between every two adjacent said trenched gates than edges of said mesa area near said trenched gates.

19. The semiconductor power device of claim 1, wherein said tilt-angle implanted drift regions are disposed above trench bottom of said trenched gates.

20. A method for manufacturing a semiconductor power device comprising the steps of:

opening a plurality of gate trenches in an epitaxial layer of a first conductivity type;

carrying out angle ion implantation of said first conductivity type dopant above said gate trenches and diffusing it to form tilt-angle implanted drift region in upper portion of said epitaxial layer and between every two adjacent of said gate trenches, wherein the doping concentration of said tilt-angle implanted drift region is higher than that of said epitaxial layer;

forming a first gate oxide layer covering inner surface of said gate trenches and top surface of said epitaxial layer;

depositing a first doped poly-silicon layer onto said first gate oxide layer and carrying out dry etching of said first doped poly-silicon layer to a pre-determined depth;

carrying out wet etching of said first gate oxide layer removing it from top surface of said epitaxial layer and from sidewalls of upper portion of said gate trenches to expose the top surface of said first doped poly-silicon layer;

growing a second gate oxide layer which is thinner than said first gate oxide layer onto sidewalls of said upper portion of said gate trenches, covering top surface of said first doped poly-silicon layer and said first gate oxide layer;

depositing a second doped poly-silicon layer onto said second gate oxide layer and etching back said second doped poly-silicon layer leaving it within said gate trenches;

carrying out ion implantation of a second conductivity type dopant opposite to said first conductivity type and diffusing it to form body region in upper portion of said epitaxial layer surrounding said gate trenches over said tilt-angle implanted drift regions;

carrying out ion implantation of said first conductivity type dopant and diffusing it to form source regions in upper portion of said epitaxial layer surrounding said gate trenches over said body region, wherein said source regions have a higher doping concentration than said epitaxial layer;

depositing a layer of NSG and a layer of BPSG successively onto entire top surface;

providing a trench mask and carrying out dry oxide etching and dry silicon etching successively to open a contact trench between every two adjacent of said gate trenches through said BPSG layer, said NSG layer, said source region and into said body region;

carrying out angle ion implantation of said second conductivity type dopant to form ohmic contact doped region surrounding bottom and sidewall of each said contact trench below said source region;

performing a step of RTA and carrying out dry silicon etching to make said contact trench further extending into said tilt-angle implanted drift region;

carrying out zero degree ion implantation optionally and angle ion implantation of said first conductivity type dopant to form barrier height enhancement region with lower doping concentration than said epitaxial layer surrounding bottom and sidewall of each said contact trench below said ohmic contact doped region followed by a step of RTA;

depositing a barrier layer overlying inner surface of said contact trenches and top surface of said BPSG layer followed by performing a step of RTA;

depositing metal material onto said barrier layer and etching back said metal material leaving it within said contact trenches;

etching back said barrier layer removing it from top surface of said BPSG layer;

depositing a front metal layer onto top surface of said BPSG layer and covering said metal material and said barrier layer.

21. The method of claim 20, wherein said barrier layer is Ti/TiN or Co/TiN or Ta/TiN.

22. The method of claim 20, wherein said metal material is tungsten material.

23. The method of claim 20, wherein said front metal layer is Ti/Al alloys, Ti/Ni/Ag or Cu.

24. The method of claim 20, wherein etching back said second doped poly-silicon layer comprising CMP or dry etching.