APPARATUS WITH CAPACITIVE COUPLING AND ASSOCIATED METHODS

• US 20120037985A1
• Filed: 08/16/2010
• Published: 02/16/2012
• Est. Priority Date: 08/16/2010
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Smith, Michael
• Application Number:
  US12/857,277
• Publication Number:
  US 20120037985A1
• Time in Patent Office: Days
• US Class Current: 257/336
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Transistors are described, along with methods and systems that include them. In one such transistor, a field plate is capacitively coupled between a first terminal and a second terminal. A potential in the field plate modulates dopant in a diffusion region in a semiconductor material of the transistor. Additional embodiments are also described.

Claims

1. A transistor comprising:

a first terminal;

a second terminal; and

a field plate capacitively coupled between the first terminal and the second terminal.

2. The transistor of claim 1, wherein the first terminal, the second terminal and the field plate each comprise metal.

3. The transistor of claim 1, wherein the first terminal, the second terminal and the field plate each include at least one of aluminum, copper, tungsten, or polysilicon.

4. The transistor of claim 1, wherein:

the first terminal is a gate terminal coupled to a gate over an active area in a semiconductor material; and

the second terminal is a drain terminal coupled to a diffusion region in the semiconductor material.

5. The transistor of claim 1, wherein:

the first terminal is a gate terminal coupled to a gate over an active area in a semiconductor material; and

the second terminal is a source terminal coupled to a diffusion region in the semiconductor material.

6. The transistor of claim 4, wherein the diffusion region comprises a drain extension region.

7. A transistor comprising:

a gate terminal coupled to a gate over an active area in a semiconductor material;

a drain terminal coupled to a first diffusion region in the semiconductor material;

a source terminal coupled to a second diffusion region in the semiconductor material; and

a field plate capacitively coupled between the gate terminal and the drain terminal.

8. The transistor of claim 7, wherein the first diffusion region comprises a drain extension region.

9. The transistor of claim 7, wherein:

each terminal has a head that extends laterally; and

the field plate is floating and capacitively coupled between the head of the gate terminal and the head of the drain terminal.

10. The transistor of claim 7, wherein the gate terminal is U-shaped and is adjacent to a plurality of sides of the field plate.

11. The transistor of claim 7, wherein the drain terminal is U-shaped and is adjacent to a plurality of sides of the field plate.

12. The transistor of claim 7, wherein:

edges of the field plate are irregular; and

edges of the drain terminal are irregular.

13. The transistor of claim 12, wherein the irregular edges of the field plate comprise a sawtooth pattern.

14. The transistor of claim 7, wherein:

edges of the field plate are irregular; and

edges of the gate terminal are irregular.

15. The transistor of claim 7, wherein:

edges of the field plate are irregular; and

edges of the source terminal are irregular.

16. The transistor of claim 7, wherein the field plate comprises individual lines connected together by crossbeams.

17. The transistor of claim 7, wherein the field plate is substantially rectangular.

18. The transistor of claim 17, wherein the field plate has straight edges and heads of the terminals have substantially straight edges.

19. The transistor of claim 7, wherein the field plate comprises a single block of metal.

20. The transistor of claim 19, wherein the block of metal has three irregular edges adjacent to and facing a head of the gate terminal.

21. The transistor of claim 7, wherein the field plate includes fingers extending from its edges towards heads of at least two of the terminals, and wherein the heads of the at least two of the terminals include fingers that are interdigitally arranged with the metal fingers extending from the field plate.

22. The transistor of claim 7, wherein the field plate has a substantially straight edge that faces a substantially straight edge of a head of the drain terminal.

23. The transistor of claim 22, further comprising another field plate capacitively coupled between the gate terminal and the source terminal.

24. A method comprising:

coupling a first voltage to a first terminal of a transistor; and

coupling a second voltage to a second terminal of the transistor, wherein a third potential is induced in a field plate capacitively coupled between the first terminal and the second terminal that modulates dopant in a diffusion region in a semiconductor material of the transistor.

25. The method of claim 24, wherein:

coupling a first voltage further comprises coupling a low voltage to a gate terminal of the transistor; and

coupling a second voltage further comprises coupling a high voltage that is higher than the low voltage to a drain terminal of the transistor.

26. The method of claim 25, wherein the low voltage is less than about one volt and the high voltage is greater than about 20 volts.

27. The method of claim 24, wherein the third potential is between the first voltage and the second voltage.

28. The method of claim 24, wherein the dopant in a drain extension region of the diffusion region is modulated.

29. A system comprising:

a plurality of transistors, each transistor comprising

a first terminal;

a second terminal; and

a field plate capacitively coupled between the first terminal and the second terminal, wherein at least one of the field plates in the plurality of transistors has a geometry that is different from geometries of the other field plates in the plurality of transistors.

30. The system of claim 29, wherein, for at least one of the plurality of transistors:

the field plate is capacitively coupled between a gate terminal and a drain terminal of the transistor; and

the field plate is located over a drain extension region in a semiconductor material of the transistor.

31. The system of claim 29, wherein, for at least one of the plurality of transistors:

an edge of the field plate is irregular; and

an edge of the first terminal is irregular, and the irregular edge of the first terminal faces the irregular edge of the field plate.