LOW HARMONIC RF SWITCH IN SOI

• US 20120038024A1
• Filed: 08/10/2010
• Published: 02/16/2012
• Est. Priority Date: 08/10/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: DANG, Dinh, DUNN, James S., JOSEPH, Alvin J., BOTULA, Alan B., LINDGREN, Peter J.
• Granted Patent: US 8,674,472 B2
• Time in Patent Office: Days
• US Class Current: 257/510
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 27/0738 in combination with resistors only
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

Claims

1. A method of fabricating a semiconductor structure, comprising:

forming at least one trench through an insulator layer, wherein the at least one trench is adjacent a device formed in an active region on the insulator layer; and

forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

2. The method of claim 1, wherein the forming the at least one cavity comprises isotropically etching the substrate through the at least one trench.

3. The method of claim 2, wherein the isotropic etching comprises etching a material of the substrate selective to a material of the insulator layer.

4. The method of claim 2, further comprising filling the at least one trench with a dielectric material without filling the at least one cavity with the dielectric material.

5. The method of claim 2, wherein the at least one cavity interrupts an interface between the substrate and the insulator layer directly beneath the device.

6. The method of claim 2, wherein the forming at least one trench comprises anisotropically etching the insulator layer.

7. The method of claim 1, wherein the at least one trench comprises a plurality of trenches around a perimeter of the device, and further comprising providing a spacing between adjacent ones of the plurality of trenches of about ten to twenty times a width of one of the plurality of trenches.

8. The method of claim 1, wherein the device comprises a radio frequency switch comprising a plurality of polysilicon lines on the active region.

9. The method of claim 1, further comprising damaging regions of the substrate under a passive device or interconnect.

10. The method of claim 9, wherein the damaging regions of the substrate comprises:

forming at least one other trench in the insulator layer; and

implanting an inert ion into the regions of the substrate.

11. A method of fabricating a semiconductor structure, comprising:

forming a semiconductor-on-insulator (SOI) wafer including a silicon substrate, an insulator layer on the substrate, and an active semiconductor layer on the insulator layer;

forming an active field effect transistor (FET) device in the active semiconductor layer; and

disrupting an interface between the substrate and the insulator layer at a location directly underneath the active FET device.

12. The method of claim 11, wherein the disrupting the interface between the substrate and the insulator layer comprises forming at least one cavity in the substrate beneath the insulator layer and at least partially vertically aligned with the active FET device.

13. The method of claim 12, wherein the forming the at least one cavity in the substrate comprises:

forming at least one trench in the insulator layer adjacent the active FET device; and

performing an isotropic etch of the substrate through the at least one trench.

14. The method of claim 13, further comprising forming a barrier layer over the active FET device.

15. The method of claim 11, further comprising:

forming a passive device in the wafer; and

damaging regions of the substrate adjacent the passive device by implanting inert ions into the regions of the substrate.

16. A semiconductor structure, comprising:

a substrate;

an insulator layer on the substrate;

an active device formed in an active semiconductor layer on the insulator layer;

at least one trench extending through the insulator layer; and

at least one cavity in the substrate, wherein the at least one cavity is below the insulator layer and extends laterally from the at least one trench to a location that is vertically aligned with the active device.

17. The structure of claim 16, wherein the at least one trench is filled with dielectric material.

18. The structure of claim 16, wherein:

the active device comprises a radio frequency (RF) switch including a plurality of polysilicon lines on the active semiconductor layer; and

the at least one trench comprises a plurality of trenches around a perimeter of the RF switch.

19. The structure of claim 18, wherein a spacing between adjacent ones of the plurality of trenches is about ten to twenty times a width of one of the plurality of trenches.

20. The structure of claim 16, wherein at least one cavity reduces substrate coupling between the active device and the substrate.