Semiconductor Device and Method of Forming Wafer-Level Multi-Row Etched Leadframe With Base Leads and Embedded Semiconductor Die

• US 20120038064A1
• Filed: 10/28/2011
• Published: 02/16/2012
• Est. Priority Date: 08/16/2010
• Status: Active Grant

• Current Assignee: Stats Chippac Limited
• Original Assignee: Stats Chippac Limited
• Inventors: Camacho, Zigmund R., Espiritu, Emmanuel A., Bathan, Henry D., Merilo, Dioscoro A.
• Granted Patent: US 8,993,376 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/4832 Etching a temporary substrate after encapsulation process to form leads
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81411 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/81424 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/81439 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/81444 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/81455 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/81805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/83805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/85411 : Tin (Sn) as principal constituent
• CPC Class Codes: H01L 2224/85424 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85439 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85447 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/85455 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06558 : the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1029 : the support being a lead frame
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 : Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49582 : Metallic layers on lead frames
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1432 : Central processing unit [CPU]
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/14335 : Digital signal processor [DSP]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1579 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A semiconductor device has a base substrate with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base substrate. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base substrate and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base substrate. A portion of the second surface of the base substrate is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.

Claims

1. A method of making a semiconductor device, comprising:

providing a base substrate having first and second opposing surfaces;

removing a first portion of the base substrate that extends from the first surface partially but not completely through the base substrate to form a plurality of cavities such that a second portion of the base substrate between the cavities forms a first set of base leads and a second set of base leads;

mounting a first semiconductor die over the first set of base leads and between the second set of base leads;

depositing an encapsulant over the first semiconductor die and base substrate;

removing a third portion of the base substrate to separate the first and second set of base leads; and

forming an interconnect structure over the encapsulant and electrically connected to first and second sets of base leads.

2. The method of claim 1, wherein the first set of base leads has a different height than the second set of base leads.

3. The method of claim 1, wherein the first set of base leads has a height similar to a height of the second set of base leads.

4. The method of claim 1, further including:

stacking a second semiconductor die over the first semiconductor die prior to depositing the encapsulant; and

electrically connecting the second semiconductor die to the interconnect structure and first or second set of base leads.

5. The method of claim 1, wherein the first set of base leads provides a vertical interconnect through the encapsulant around the first semiconductor die.

6. The method of claim 1, further including forming a concave capture pad over the first set of base leads.

7. A method of making a semiconductor device, comprising:

providing a base substrate;

removing a first portion of the base substrate to form a plurality of cavities and a plurality of base leads between the cavities;

mounting a first semiconductor die to the base substrate;

depositing a first insulating layer over the first semiconductor die and base substrate;

removing a second portion of the base substrate to separate the base leads; and

forming an interconnect structure over the first insulating layer and electrically connected to the base leads.

8. The method of claim 7, further including mounting the first semiconductor die over a first set of the base leads and between a second set of the base leads.

9. The method of claim 8, further including forming a concave capture pad over the first set of base leads.

10. The method of claim 7, further including:

forming a plurality of openings in the base substrate; and

mounting the first semiconductor die over the openings in the base substrate.

11. The method of claim 7, further including forming a second insulating layer over the base substrate prior to mounting the first semiconductor die.

12. The method of claim 7, further including:

stacking a second semiconductor die over the first semiconductor die prior to depositing the first insulating layer; and

electrically connecting the second semiconductor die to the interconnect structure and base leads.

13. The method of claim 7, further including:

stacking a plurality of the semiconductor devices; and

electrically connecting the stacked semiconductor devices through the interconnect structure and base leads.

14. A method of making a semiconductor device, comprising:

providing a base substrate having a plurality of base leads;

mounting a first semiconductor die to the base substrate;

depositing an insulating layer over the first semiconductor die and base substrate;

removing a portion of the base substrate to separate the base leads; and

forming an interconnect structure over the insulating layer and base leads.

15. The method of claim 14, further including mounting the first semiconductor die over a first set of the base leads and between a second set of the base leads.

16. The method of claim 15, further including forming a concave capture pad over the first set of base leads.

17. The method of claim 14, further including forming a concave capture pad in the base substrate.

18. The method of claim 14, further including:

forming a plurality of openings in the base substrate; and

mounting the first semiconductor die over the openings in the base substrate.

19. The method of claim 14, further including:

stacking a second semiconductor die over the first semiconductor die prior to depositing the insulating layer; and

electrically connecting the second semiconductor die to the interconnect structure and base leads.

20. The method of claim 14, further including:

stacking a plurality of the semiconductor devices; and

electrically connecting the stacked semiconductor devices through the interconnect structure and base leads.

21. A semiconductor device made by a process, comprising:

a base substrate having a plurality of base leads;

a first semiconductor die mounted to the base substrate;

an insulating layer deposited over the first semiconductor die and base substrate, wherein a portion of the base substrate is removed to separate the base leads; and

an interconnect structure formed over the insulating layer and base leads.

22. The semiconductor device of claim 21, wherein the first semiconductor die is mounted over a first set of the base leads and between a second set of the base leads.

23. The semiconductor device of claim 22, further including a concave capture pad formed over the first set of base leads.

24. The semiconductor device of claim 21, wherein a first set of the base leads provides a vertical interconnect through the insulating layer around the first semiconductor die.

25. The semiconductor device of claim 21, further including a second semiconductor die stacked over the first semiconductor die and electrically connected to the interconnect structure and base leads.