SYMMETRICALLY OPERATING SINGLE-ENDED INPUT BUFFER DEVICES AND METHODS

• US 20120038422A1
• Filed: 10/10/2011
• Published: 02/16/2012
• Est. Priority Date: 12/18/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Amirabadi, Yadollah Eslami
• Granted Patent: US 8,395,956 B2
• Time in Patent Office: Days
• US Class Current: 330/254
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03F 2203/45091 Two complementary type differential amplifiers are paralleled, e.g. one of the p-type and one of the n-type
• CPC Class Codes: H03F 2203/45296 the AAC comprising one or more discrete capacitive elements, e.g. a transistor coupled as capacitor
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance

Abstract

Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One example buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor to mimic the second input node transitioning in the direction opposite to the transition of the input signal.

Claims

1. A differential amplifier comprising:

a first voltage supply and a second voltage supply;

a first transistor coupled between the first and second voltage supplies, the first transistor having an input node adapted to receive an input signal; and

a second transistor coupled between the first and second voltage supplies, the second transistor having a first terminal and a second input node adapted to receive a reference signal, the first input node of the first transistor being capacitively coupled to the first terminal of the second transistor to charge and discharge the first terminal of the second transistor responsive to the input signal transitioning.