Transmission Interface and System Using the Same

• US 20120038497A1
• Filed: 08/12/2010
• Published: 02/16/2012
• Est. Priority Date: 08/12/2010
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Tsai, Chung-Hung, Ku, Wei-Cheng, Li, Chun-Nan, Chen, Yi-Hsi
• Granted Patent: US 8,648,739 B2
• Time in Patent Office: Days
• US Class Current: 341/100
• CPC Class Codes: G09G 2370/10 Use of a protocol of communication by packets in interfaces along the display data pipeline
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: H04N 21/43632 involving a wired protocol, e.g. IEEE 1394 high-speed IEEE 1394 serial bus H04L12/40052
• CPC Class Codes: H04N 5/04 Synchronising for television systems using pulse code modulation H04N7/56

Abstract

A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input data stream to parallel input data and converts the serial clock to a parallel clock. The serial input data stream has a full swing form. The decoding unit receives and decodes the parallel input data and generates an input data signal according to the decoded parallel input data.

Claims

1. (FIG. 2A) A transmission interface (11) comprising:

a first pin (P1) and a second pin (P2);

a conversion unit (110) for receiving a first serial input data stream (SD) via the first pin (P1), receiving a serial clock (SC) via the second pin (P2), converting the first serial input data stream (SD) to parallel input data (PD110), and converting the serial clock (SC) to a parallel clock (PC110), wherein the first serial input data stream has a full swing form; and

a decoding unit (111) for receiving and decoding the parallel input data (PD110) and generating an input data signal (DATA) according to the decoded parallel input data

2. (FIG. 2B) The transmission interface as claimed in claim 1, wherein the conversion unit further receives a serial synchronization data stream (SSYNC), which has the full swing form and is merged with the first serial input data stream, via the first pin and converts the serial synchronization data stream to parallel synchronization data (PSYNC).

3. The transmission interface as claimed in claim 2, wherein the decoding unit further receives and decodes the parallel synchronization data (PSYNC) and generates a first synchronization signal (VSYNC111) and a second synchronization signal (HSYNC111) according to the decoded parallel synchronization data and the parallel clock.

4. The transmission interface as claimed in claim 1, wherein the serial clock has the full swing form.

5. The transmission interface as claimed in claim 1, wherein the first serial input data stream is transmitted in a packet format.

6. (FIG. 1B) The transmission interface as claimed in claim 1 further comprising:

a third pin (P3) for receiving a digital power (DP); and

a fourth pin (P4) coupled to a ground (G).

7. The transmission interface as claimed in claim 6 further comprising a fifth pin for receiving a second serial input data stream.

8. The transmission interface as claimed in claim 6 further comprising:

a fifth pin for receiving a second serial input data stream;

a sixth pin for receiving a third serial input data stream; and

a seventh pin for receiving a fourth serial input data stream.

9. (FIG. 1A, 2A, 2B) An electronic system comprising:

a transmission device (10) for generating a first serial input data stream (SD) and a serial clock (SC), wherein the first serial input data stream has a full swing form;

a transmission interface (11) for receiving the first serial input data stream and the serial clock and comprising;

a first pin (P1) and a second pin (P2);

a first conversion unit (110) for receiving the first serial input data stream via the first pin, receiving the serial clock via the second pin, converting the first serial input data stream to first parallel input data (PD110), and converting the serial clock to a first parallel clock (PC110); and

a decoding unit (111) for receiving and decoding the first parallel input data and generating an input data signal (DATA) according to the decoded parallel input data; and

a processing device (12) for receiving and processing the input data signal.

10. (FIG. 2B) The electronic system as claimed in claim 9, wherein the transmission device further generates a serial synchronization data stream (SSYNC), and the first conversion unit further receives the serial synchronization data stream, which has the full swing form and is merged with the first serial input data stream, via the first pin and converts the serial synchronization data stream to parallel synchronization data (PSYNC).

11. The electronic system as claimed in claim 10, wherein the decoding unit further receives and decodes the parallel synchronization data and generates a first synchronization signal (VSYNC111) and a second synchronization signal (HSYNC111) according to the decoded parallel synchronization data and the first parallel clock.

12. The electronic system as claimed in claim 11, wherein the processing device processes the input data signal according to at least one of the first and second synchronization signals.

13. The electronic system as claimed in claim 11, wherein the transmission device comprises a second conversion unit (100) which receives second parallel data (PD100), a second parallel clock (PC100), a third synchronization signal (VSYNC100), and a fourth synchronization signal (HSYNC100), converts the second parallel data to the first serial input data stream, converts the second parallel clock to the serial clock, and generates the serial synchronization data stream according to the third and fourth synchronization signals.

14. (FIG. 2A) The electronic system as claimed in claim 9, wherein the transmission device generates second parallel data (PD100), a second parallel clock (PC100), a first synchronization signal (VSYNC100), and a second synchronization signal (HSYNC100) and comprises a second conversion unit which converts the second parallel data to the first serial input data stream, converts the second parallel clock to the serial clock.

15. (FIG. 2A) The electronic system as claimed in claim 14, wherein the transmission device provides the first (VSYNC100) and second (HSYNC100) synchronization signals to the processing device (12), and the processing device processes the input data signal (DATA) according to at least one of the first and second synchronization signals (VSYNC100, HSYNC100).

16. The electronic system as claimed in claim 9, wherein the serial clock has the full swing form.

17. The electronic system as claimed in claim 9, wherein the first serial input data stream is transmitted in a packet format.

18. The electronic system as claimed in claim 9, wherein the electronic system is a camera system.

19. The electronic system as claimed in claim 9, wherein the transmission device is an image sensor which detects images and provides the first serial input data stream (SD) according to the detected images.

20. (FIG. 1B) The electronic system as claimed in claim 9 further comprising a receiving device, wherein the transmission interface and the processing device are combined into the receiving device.

21. The electronic system as claimed in claim 18, wherein the transmission interface further comprises:

a third pin (P3) for receiving a digital power; and

a fourth pin (P4) coupled to a ground.

22. The electronic system as claimed in claim 21 further comprising a fifth pin for receiving a second serial input data stream.

23. The electronic system as claimed in claim 21 further comprising:

a fifth pin for receiving a second serial data stream;

a sixth pin for receiving a third serial input data stream; and

a seventh pin for receiving a fourth serial input data stream.