Semiconductor device with shortened data read time

• US 20120039144A1
• Filed: 08/10/2011
• Published: 02/16/2012
• Est. Priority Date: 08/13/2010
• Status: Abandoned Application

• Current Assignee: PS4 Luxco S.a.r.l.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Nagamine, Hisayuki, Tobori, Hidenori
• Application Number:
  US13/137,388
• Publication Number:
  US 20120039144A1
• Time in Patent Office: Days
• US Class Current: 365/207
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A semiconductor device includes: a plurality of memory cell arrays arranged along a predetermined direction; a plurality of bit lines to read data stored in a plurality of memory elements; a plurality of sense amplifier sections that amplify potentials appearing on selected bit lines, that amplify potentials in opposite phase to the potentials, and that output data signals and inverted data signals; a data output circuit that outputs the data to an external circuit based on the data signals and the inverted data signals; and a plurality of local signal lines extending parallel to the predetermined direction, to transmit the data signal and the inverted data signals to the data output circuit, wherein the local signal lines include two adjacent signal lines which are positionally switched around in a direction perpendicular to the predetermined direction alternately at predetermined intervals.

Claims

1. A semiconductor device comprising:

a plurality of memory cell arrays arranged along a predetermined direction, each of said memory cell arrays including a memory elements;

a plurality of bit lines associated with said memory cell arrays, to read data stored in said memory elements;

a plurality of sense amplifier sections associated with said memory cell arrays that amplify potentials which correspond to said data, appearing on selected bit lines, that amplify potentials in opposite phase to said potentials, that output data signals representing the amplified potentials corresponding to said data in a direction which is different from said predetermined direction, and that output inverted data signals which are in opposite phase to said data signals in a direction which is opposite to the is direction in which said data signals are output;

a data output circuit that outputs said data to an external circuit based on said data signals and said inverted data signals; and

a plurality of local signal lines extending parallel to said predetermined direction, to transmit said data signal and said inverted data signals to said data output circuit;

wherein said local signal lines include two adjacent signal lines which are positionally switched around in a direction perpendicular to said predetermined direction alternately at predetermined intervals.

2. The semiconductor device according to claim 1, wherein said predetermined intervals represent the respective lengths of said memory cell arrays in said predetermined direction.

3. The semiconductor device according to claim 1, wherein said predetermined intervals represent one half of the lengths of said local signal lines.

4. A semiconductor device comprising:

a plurality of memory cell arrays arranged along a predetermined direction, each of said memory cell arrays including a memory elements;

a plurality of bit lines associated with said memory cell arrays, to read data stored in said memory elements;

a plurality of sense amplifier sections associated with said memory cell arrays that amplify potentials which correspond to said data, appearing on selected bit lines, that amplify potentials in opposite phase to said potentials, that output data signals representing the amplified potentials corresponding to said data in a direction which is different from said predetermined direction, and that output inverted data signals which are in opposite phase to said data signals in a direction which is opposite to the direction in which said data signals are output;

a data output circuit that outputs said data to an external circuit based on said data signals and said inverted data signals;

a plurality of local signal lines extending parallel to said predetermined direction, to transmit said data signal and said inverted data signals to said data output circuit, said local signal lines including pairs of two adjacent local signal lines; and

a shield line disposed between said pairs of two adjacent local signal lines, said shield line being connected to a power supply potential or a ground potential.