CONVERTER AND CONVERTER CONTROL METHOD

• US 20120039378A1
• Filed: 08/16/2010
• Published: 02/16/2012
• Est. Priority Date: 08/16/2010
• Status: Active Grant

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: Nakayama, Kazuaki
• Granted Patent: US 8,379,412 B2
• Time in Patent Office: Days
• US Class Current: 375/226
• CPC Class Codes: H02M 1/0041 Control circuits in which a clock signal is selectively enabled or disabled
• CPC Class Codes: H02M 1/0058 by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826
• CPC Class Codes: H02M 3/01 Resonant DC/DC converters
• CPC Class Codes: H02M 3/33571 Half-bridge at primary side of an isolation transformer
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Techniques are generally described for a converter including a PLL and a pulse deleting circuit. The pulse deleting circuit is configured to delete a pulse from one of the inputs to the PLL when a filtered output in the PLL falls below a first reference level and an unlocked state of the PLL is detected in response to a phase lag of one of the first and second pulse inputs with respect to the other. The pulse deleting circuit may also be configured to delete one pulse of the other of the first and second pulse inputs when the filtered output exceeds a second reference level and the unlocked state of the PLL is detected in response to a phase lead of the one of the first and second pulse inputs with respect to the other.

Claims

1. A converter comprising:

a PLL (Phase-Locked Loop) circuit including a detector circuit, a lock detection circuit, a filter circuit and an oscillator circuit, wherein the detector circuit is configured to detect a phase error between a first pulse input and a second pulse input and to generate an error signal indicative of the detected phase error, the filter circuit is configured to filter the error signal and to provide a filtered error signal, the lock detection circuit is configured to detect a locked or unlocked state of the PLL circuit in response to the error signal, and the oscillator circuit is configured to produce an oscillator output signal in response to the filtered error signal;

a pulse control circuit configured to receive the oscillator output signal and a feedback signal, and to generate a drive signal in response thereto;

a comparator circuit configured to receive and evaluate the filtered error signal to determine when the filtered error signal either falls below a first reference level or exceeds a second reference level that is higher than the first reference level; and

a pulse deleting circuit configured to receive the drive signal and to provide the first pulse input in response thereto, and also configured to receive a resonant current measurement from a primary side of a transformer circuit and to provide the second pulse input in response thereto,

wherein the pulse deleting circuit is configured to delete one pulse of one of the first and second pulse inputs when the comparator circuit detects the filtered error signal falling below the first reference level and the lock detection circuit detects the unlocked state in response to a phase lag of the one of the first and second pulse inputs with respect to the other of the first and second pulse inputs detected by the detector circuit,

and wherein the pulse deleting circuit is configured to delete one pulse of the other of the first and second pulse inputs when the comparator circuit detects that the filtered error signal exceeds the second reference level and the lock detection circuit detects the unlocked state in response to a phase lead of the one of the first and second pulse inputs with respect to the other of the first and second pulse inputs detected by the detector circuit.

2. The converter of claim 1, further comprising:

a second comparator circuit configured to supply, to the pulse deleting circuit, an edge-triggered pulse signal having an edge occurring about a zero-crossing time of a resonant current of the resonant current measurement.

3. The converter of claim 1, further comprising:

a feedback circuit configured to provide the feedback signal to the pulse control circuit in response to an output from a secondary side of the transformer circuit.

4. The converter of claim 1, further comprising:

a feedback circuit configured to provide the feedback signal to the pulse control circuit in response to the resonant current measurement.

5. The converter of claim 4, wherein the feedback circuit includes an output varying function to vary the feedback signal in response to an external signal.

6. The converter of claim 1, wherein the secondary side of the transformer circuit corresponds to a DC output to be applied to a load.

7. The converter of claim 1, wherein the secondary side of the transformer circuit corresponds to an AC output to be applied to a load.

8. The converter of claim 1, further comprising:

a switching circuit that is configured to drive the primary side of the transformer circuit to transmit power to the secondary side by alternately switching at a switching frequency of the drive signal,

wherein the PLL circuit is configured to adapt the PLL operation to substantially match the switching frequency to a resonant frequency of the converter.

9. The converter of claim 8, further comprising:

a second comparator circuit configured to supply, to the pulse deleting circuit, a first edge-triggered pulse signal having an edge occurring about a zero-crossing time of a resonant current of the resonant current measurement,

wherein the pulse control circuit generates, as the drive signal, a second edge-triggered pulse signal having a phase substantially matching a phase of the first edge-triggered pulse signal.

10. A method to control a converter, the method comprising:

receiving, by a pulse deleting circuit, a drive signal from a pulse control circuit and supplying a first pulse input in response thereto;

receiving, by the pulse deleting circuit, a resonant current from a primary side of a transformer circuit and supplying a second pulse input in response thereto;

detecting, by a comparator circuit, when a filtered error signal of a PLL (Phase-Locked Loop) circuit falls below a first reference level and asserting a first control signal in response thereto;

detecting, by the comparator circuit, when the filtered error signal of the PLL circuit exceeds a second reference level that is higher than the first reference level, and asserting a second control signal in response thereto;

detecting, by a lock detection circuit of the PLL circuit, an unlocked state of the PLL circuit in response to a phase lag or phase lead of one of the first and second pulse inputs with respect to the other of the first and second pulse inputs and asserting an unlock detection signal in response thereto;

deleting, by the pulse deleting circuit, one pulse of one of the first and second pulse inputs based on the control signal and the unlock detection signal from the PLL circuit when the first control signal and the unlock detection signal are both asserted; and

deleting, by the pulse deleting circuit, one pulse of the other of the first and second pulse inputs based on the control signal and the unlock detection signal from the PLL circuit when the second control signal and the unlock detection signal are both asserted.

11. The method of claim 10, further comprising:

supplying an edge-triggered pulse signal having an edge occurring about a zero-crossing time of the resonant current, from a second comparator circuit to the pulse deleting circuit.

12. The method of claim 10, further comprising:

providing a feedback signal to the pulse control circuit from a feedback circuit in response to an output from a secondary side of the transformer circuit.

13. The method of claim 10, further comprising:

providing a feedback signal to the pulse control circuit from a feedback circuit in response to the resonant current.

14. The method of claim 13, wherein the providing the feedback signal includes varying the feedback signal by an output varying function of the feedback circuit in response to an external signal.

15. The method of claim 10, further comprising:

applying a DC output, corresponding to a secondary side of the transformer circuit, to a load.

16. The method of claim 10, further comprising:

applying an AC output, corresponding to a secondary side of the transformer circuit, to a load.

17. The method of claim 10, further comprising:

transmitting power to a secondary side of the transformer circuit by selectively actuating a switching circuit in response to a drive signal from the pulse control circuit; and

adapting PLL operation by the PLL circuit to substantially match a switching frequency of the switching circuit to a resonant frequency of the converter.

18. The method of claim 17, further comprising:

supplying a first edge-triggered pulse signal having an edge occurring about a zero-crossing time of the resonant current, from a second comparator circuit to the pulse deleting circuit; and

generating, as the drive signal from the pulse control circuit, a second edge-triggered pulse signal having a phase substantially matching a phase of the first edge-triggered pulse signal.

19. A method to control a converter including a PLL (Phase-Locked Loop), the method comprising:

deleting one pulse of one of first and second pulse inputs to the PLL when a filtered output obtained through phase detection in the PLL falls below a first reference level and an unlocked state of the PLL is detected in response to a phase lag of one of the first and second pulse inputs with respect to the other; and

deleting one pulse of the other of the first and second pulse inputs when the filtered output exceeds a second reference level and the unlocked state of the PLL is detected in response to a phase lead of the one of the first and second pulse inputs with respect to the other.

20. The method of claim 19, wherein at least one of the deleting one pulse of the one of the first and second pulse inputs and the deleting one pulse of the other of the first and second pulse inputs deletes one pulse by inserting a zero-pulse or a low-level pulse to the one or the other of the first and second pulse inputs.