Methods and Apparatus for Measuring Analytes Using Large Scale FET Arrays

• US 20120040844A1
• Filed: 02/08/2011
• Published: 02/16/2012
• Est. Priority Date: 12/14/2006
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Rothberg, Jonathan M., Hinz, Wolfgang, Johnson, Kim L., Bustillo, James
• Granted Patent: US 8,269,261 B2
• Time in Patent Office: Days
• US Class Current: 506/7
• CPC Class Codes: C12Q 1/6818 involving interaction of two or more labels, e.g. resonant energy transfer
• CPC Class Codes: C12Q 1/6874 involving nucleic acid arrays, e.g. sequencing by hybridisation
• CPC Class Codes: C12Q 2533/101 Primer extension
• CPC Class Codes: C12Q 2565/301 Pyrophosphate (PPi)
• CPC Class Codes: C12Q 2565/607 being a sensor, e.g. electrode
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G01N 33/54373 involving physiochemical end-point determination, e.g. wave-guides, FETS, gratings
• CPC Class Codes: G01N 33/5438 Electrodes
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01073 Tantalum [Ta]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: Y10T 436/22 Hydrogen, per se

Abstract

Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Claims

1-106. -106. (canceled)

107. An apparatus comprising:

a sensor array of at least 10⁵ sensors each comprising at least one chemFET having a gate oxide with a characteristic thickness, a floating gate, and a characteristic threshold voltage;

wherein the characteristic threshold voltage of each chemFET is affected by trapped charge; and

wherein the characteristic thickness of the gate oxide is selected to reduce the trapped charge in the sensor.

108. The apparatus of claim 107, wherein trapped charge in the sensor flows to a substrate associated with the sensor as a result of the characteristic thickness of the gate oxide.

109. The apparatus of claim 107, wherein the gate oxide thickness is permissible to trapped charge flowing to a substrate associated with a respective sensor.

110. The apparatus of claim 107, where the thickness of the gate oxide is approximately 75 Angstroms.

111. The apparatus of claim 107, where the characteristic threshold voltage of a respective chemFET sensor is similar to that of characteristic threshold voltages for other chemFETs in the sensor array.

112. The apparatus of claim 107, further comprising control circuitry configured to detect output signals from the sensors, wherein the output signal depends at least in part on the characteristic threshold voltage for a respective sensor of the sensor array.

113. The apparatus of claim 112, wherein the output signals from the sensors are substantially similar in response.

114. The apparatus of claim 112, wherein the sensors of the sensor array are substantially similar in sensitivity.

115. The apparatus of claim 112, wherein the control circuitry further comprises at least one analog-to-digital converter.

116. The apparatus of claim 112, wherein the sensor array and at least a portion of the control circuitry are formed on a single substrate.

117. The apparatus of claim 107, further comprising an array of reaction chambers coupled to the array of sensors.

118. The apparatus of claim 117, wherein output signals are created in response to the presence of analytes in the reaction chambers.

119. The apparatus of claim 118, wherein the analytes comprise hydrogen ions.

120. The apparatus of claim 118, wherein the analytes comprise byproducts of a chemical reaction.

121. The apparatus of claim 120, wherein the chemical reaction comprises nucleotide incorporation into a sample nucleic acid template.

122. A method for reducing trapped charge in a sensor array comprising:

providing a sensor array of at least 10⁵ sensors each comprising at least one chemFET having a gate oxide with a characteristic thickness, a floating gate, and a characteristic threshold voltage;

and

removing at least a portion of a trapped charge in the sensor array where the trapped charge flows to a substrate associated with the sensor based on the characteristic thickness of the gate oxide.

123. The method of claim 122 wherein resultant effects on the characteristic threshold voltage for respective chemFETs from the trapped charge in the sensor array are reduced by removal of at least a portion of the trapped charge.

125. The method of claim 122, wherein the gate oxide thickness is approximately 75 Angstroms.

126. A method for reducing trapped charge in a field effect transistor comprising:

providing a field effect transistor (FET) having a gate oxide with a characteristic thickness, a floating gate, and a characteristic threshold voltage;

selecting the gate oxide thickness so as to permissible to trapped charge flowing to a substrate associated with a respective sensor

and

removing at least a portion of a trapped charge in the FET where the trapped charge flows to the substrate associated with the FET based on the characteristic thickness of the gate oxide.