MULTIPROCESSOR SYSTEM-ON-A-CHIP FOR MACHINE VISION ALGORITHMS

• US 20120042150A1
• Filed: 03/29/2011
• Published: 02/16/2012
• Est. Priority Date: 08/11/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: PrimeSense Ltd (Apple Inc.)
• Inventors: Saar, Idan
• Granted Patent: US 9,075,764 B2
• Time in Patent Office: Days
• US Class Current: 712/30
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox

Abstract

A multiprocessor system includes a main memory and multiple processing cores that are configured to execute software that uses data stored in the main memory. In some embodiments, the multiprocessor system includes a data streaming unit, which is connected between the processing cores and the main memory and is configured to pre-fetch the data from the main memory for use by the multiple processing cores. In some embodiments, the multiprocessor system includes a scratch-pad processing unit, which is connected to the processing cores and is configured to execute, on behalf of the multiple processing cores, a selected part of the software that causes two or more of the processing cores to access concurrently a given item of data.

Claims

1. A multiprocessor system, comprising:

a main memory;

multiple processing cores, which are configured to execute software that uses data stored in the main memory; and

a data streaming unit, which is connected between the processing cores and the main memory and is configured to pre-fetch the data from the main memory for use by the multiple processing cores.

2. The multiprocessor system according to claim 1, wherein the data streaming unit is configured to store the data in the main memory on behalf of the multiple processing cores.

3. The multiprocessor system according to claim 1, wherein the data streaming unit comprises arbitration circuitry that is configured to resolve simultaneous accesses to the main memory that are performed on behalf of two or more of the processing cores.

4. The multiprocessor system according to claim 1, wherein the data streaming unit comprises, for each processing core, a respective front-end unit that is configured to receive from the processing core a respective list of addresses in the main memory, and to pre-fetch the data from the main memory in accordance with the list.

5. The multiprocessor system according to claim 4, and comprising a respective local memory associated with each processing core, wherein each processing core and the corresponding front-end unit are configured to exchange the data via the respective local memory.

6. The multiprocessor system according to claim 5, wherein each processing core and the corresponding front-end unit are configured to maintain the list of addresses in a circular buffer that is stored in the respective local memory.

7. The multiprocessor system according to claim 1, wherein at least the processing cores and the data streaming unit are comprised in a single integrated circuit.

8. A multiprocessor system, comprising:

a main memory;

multiple processing cores, which are configured to execute software that uses data stored in the main memory; and

a scratch-pad processing unit, which is connected to the processing cores and is configured to execute, on behalf of the multiple processing cores, a selected part of the software that causes two or more of the processing cores to access concurrently a given item of data.

9. The multiprocessor system according to claim 8, wherein the scratch-pad processing unit comprises a dedicated memory for storing the given item of data that is accessed by the two or more of the processing cores.

10. The multiprocessor system according to claim 9, wherein the scratch-pad processing unit is configured to accept scratch-pad instructions from the processing cores, to arbitrate the scratch-pad instructions and to execute the arbitrated scratch-pad instructions in the dedicated memory.

11. The multiprocessor system according to claim 8, wherein at least the processing cores and the scratch-pad processing unit are comprised in a single integrated circuit.

12. A method for data processing, comprising:

executing software, which uses data stored in a main memory, on multiple processing cores of a multiprocessor system; and

pre-fetching the data from the main memory by a data streaming unit that is connected between the processing cores and the main memory, for use by the multiple processing cores.

13. The method according to claim 12, and comprising storing the data in the main memory on behalf of the multiple processing cores by the data streaming unit.

14. The method according to claim 12, wherein pre-fetching the data comprises resolving simultaneous accesses to the main memory that are performed on behalf of two or more of the processing cores.

15. The method according to claim 12, wherein pre-fetching the data comprises providing a respective list of addresses in the main memory from each processing core to a respective front-end unit, and pre-fetching the data from the main memory by the front-end unit in accordance with the list.

16. The method according to claim 15, wherein pre-fetching the data comprises exchanging the data between each processing core and the respective front-end unit via a respective local memory that is associated with the processing core.

17. The method according to claim 16, wherein exchanging the data comprises maintaining the list of addresses in a respective circular buffer that is stored in the respective local memory.

18. The method according to claim 12, wherein at least the processing cores and the data streaming unit are comprised in a single integrated circuit.

19. A method for data processing, comprising:

executing software, which uses data stored in a main memory, on multiple processing cores of a multiprocessor system; and

using a scratch-pad processing unit that is connected to the multiple processing cores, executing on behalf of the processing cores a selected part of the software that causes two or more of the processing cores to access concurrently a given item of data.

20. The method according to claim 19, wherein executing the part of the software comprises storing the given item of data that is accessed by the two or more of the processing cores in a dedicated memory of the scratch-pad processing unit.

21. The method according to claim 20, and comprising accepting in the scratch-pad processing unit scratch-pad instructions from the processing cores, arbitrating the scratch-pad instructions, and executing the arbitrated scratch-pad instructions in the dedicated memory.

22. The method according to claim 19, wherein at least the processing cores and the scratch-pad processing unit are comprised in a single integrated circuit.