METHOD AND APPARATUS FOR SENSING A CURREN FOR VARYING IMPEDANCE LOADS

• US 20120044020A1
• Filed: 08/23/2010
• Published: 02/23/2012
• Est. Priority Date: 08/23/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Siniscalchi, Patrick P., Garg, Mayank, Jones, Roy Clifton III
• Granted Patent: US 8,143,944 B2
• Time in Patent Office: Days
• US Class Current: 330/251
• CPC Class Codes: H03F 3/2173 of the bridge type

Abstract

Recently, there has been an increased desire to measure load currents of class-D amplifiers to improve performance. The traditional solution has been to include one or more discrete components in series with the load, but this degrades performance. Here, however, circuit is provided (which includes sample-and-hold circuit) that accurately measures load currents without inhibiting performance and that is not inhibited by the phase differences between the load voltage and load current.

Claims

1. An apparatus comprising:

a class-D amplifier having a low-side recycling mode, a pair of low-side NMOS transistors, and a pair of output terminals;

a sample-and-hold (S/H) that is coupled to the pair of output terminals, wherein the S/H circuit samples a voltage on each of the pair of output terminals of the class-D amplifier when its associated low-side NMOS transistor is actuated;

a current generator that is coupled to the S/H circuit, wherein the current generator uses the voltages on the pair of output terminals sampled by the S/H circuit to minor the drain-source voltages of the pair of low-side NMOS transistors on a pair of sense transistors, and wherein the drain-source voltages mirrored on the pair of sense transistors generates a pair of sense currents; and

a current-to-voltage (I-to-V) converter that is coupled to the current generator so as to convert the sense currents to a sense voltage.

2. The apparatus of claim 1, wherein the S/H circuit further comprises:

a pair of switches, wherein each switch is coupled to at least one of the pair of output terminals, and wherein each switch is associated with at least one of the pair of low-side NMOS transistors; and

a pair of capacitors, wherein each capacitor is associated with at least one of the switches, and wherein each switch provides the voltage from its associated output terminal when its associated low-side NMOS transistor is actuated.

3. The apparatus of claim 2, wherein the ratio of sizes of each of the pair of sense transistors to its associated low-side NMOS transistor is 1:

N, wherein N is greater than or equal to 1.

4. An apparatus comprising:

an H-bridge having a first input terminal, a second input terminal, a first output terminal, and a second output terminal;

a first driver that is coupled to provide a first control signal to the first terminal of the H-bridge;

a second driver that is coupled to provide a second control signal to the second terminal of the H-bridge;

an S/H circuit that is coupled to the first driver, second driver, the first output terminal of the H-bridge, and the second output terminal of the H-bridge, wherein the S/H circuit samples a first output voltage from the first output terminal of the H-bridge based at least in part on the state of the first control signal, and wherein the S/H circuit samples a second voltage from the second output terminal of the H-bridge based at least in part on the state of the second control signal;

a current generator including;

a first amplifier having a first input terminal, a second terminal, and an output terminal, wherein the first input terminal of the first amplifier is coupled to the S/H circuit;

a second amplifier having a first input terminal, a second terminal, and an output terminal, wherein the first input terminal of the second amplifier is coupled to the S/H circuit;

a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor is coupled to the output terminal of the first amplifier;

a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein first passive electrode of the second transistor is coupled to the second passive electrode of the first transistor;

a third transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the third transistor is coupled to the output terminal of the second amplifier; and

a fourth transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein first passive electrode of the fourth transistor is coupled to the second passive electrode of the third transistor; and

an I-to-V converter that is coupled to the first passive electrodes of the first and third transistors.

5. The apparatus of claim 4, wherein the H-bridge further comprises:

a first low-side transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the first low-side transistor is coupled to the first output terminal of the H-bridge, and wherein the control electrode of the first low-side transistor is coupled to the first driver; and

a second low-side transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the second low-side transistor is coupled to the second output terminal of the H-bridge, and wherein the control electrode of the second low-side transistor is coupled to the second driver.

6. The apparatus of claim 5, wherein ratio of the sizes the second transistor to the first low-side transistor and the fourth transistor to the second low-side transistor is 1:

N, wherein N is greater than or equal to 1.

7. The apparatus of claim 6, wherein the S/H circuit further comprises:

a first switch that is coupled to the first output terminal of the H-bridge, wherein the first switch is controlled by the first control signal;

a second switch that is coupled to the second output terminal of the H-bridge, wherein the second switch is controlled by the second control signal;

a first resistor that is coupled to the first switch;

a second resistor that is coupled to the second switch;

a first capacitor that is coupled to the first resistor; and

a second capacitor that is coupled to the second resistor.

8. The apparatus of claim 7, wherein the first and second switch are each double-throw switches that are each coupled to ground, and wherein the current generator further comprises:

a third switch that is coupled to the first output terminal of the H-bridge and that is controlled by the second control signal;

a first set of resistors coupled in series with one another between the third switch and the second passive electrode of the first transistor, wherein the second input terminal of the first amplifier is coupled to a node between at least two resistors from the first set;

a fourth switch that is coupled to the second output terminal of the H-bridge and that is controlled by the first control signal; and

a second set of resistors coupled in series with one another between the fourth switch and the second passive electrode of the third transistor, wherein the second input terminal of the second amplifier is coupled to a node between at least two resistors from the second set.

9. The apparatus of claim 6, wherein the I-to-V converter further comprises a differential amplifier that outputs a differential sense voltage.

10. The apparatus of claim 6, wherein the I-to-V converter further comprises:

a current mirror that is coupled to the first passive electrode of the first transistor; and

a third amplifier having an input terminal that is coupled to the current mirror and the first passive electrode of the third transistor.

11. An apparatus comprising:

a class-D amplifier having;

a negative output terminal;

a positive output terminal;

a first NMOS transistor that is coupled to the negative output terminal at its drain and that is controlled by a first control signal;

a second NMOS transistor that is coupled to the positive output terminal at its drain and that is controlled by a second control signal;

an S/H circuit that is coupled to the negative output terminal and the positive output terminal, wherein the S/H circuit samples the voltage on the negative output terminal when the first NMOS transistor is actuated, and wherein the S/H circuit samples the voltage on the positive output terminal when the second NMOS transistor is actuated;

a current generator having;

a first amplifier having a first input terminal, a second terminal, and an output terminal, wherein the first input terminal of the first amplifier is coupled to the S/H circuit;

a second amplifier having a first input terminal, a second terminal, and an output terminal, wherein the first input terminal of the second amplifier is coupled to the S/H circuit;

a third NMOS transistor that is coupled to the output terminal of the first amplifier at its gate;

a fourth NMOS transistor that is coupled to the source of the third NMOS at its drain;

a fifth NMOS transistor that is coupled to the output terminal of the second amplifier at its gate;

a sixth NMOS transistor that is coupled to the source of the fifth NMOS at its drain; and

an I-to-V converter that is coupled to the drains of the third and fifth NMOS transistors.

12. The apparatus of claim 11, wherein ratio of the sizes the fourth NMOS transistor to the first NMOS transistor and the sixth NMOS transistor to the second NMOS transistor is 1:

N, wherein N is greater than or equal to 1.

13. The apparatus of claim 12, wherein the S/H circuit further comprises:

a first switch that is coupled to the negative output terminal, wherein the first switch is controlled by the first control signal;

a second switch that is coupled to the positive output terminal, wherein the second switch is controlled by the second control signal;

a first resistor that is coupled to the first switch;

a second resistor that is coupled to the second switch;

a first capacitor that is coupled to the first resistor; and

a second capacitor that is coupled to the second resistor.

14. The apparatus of claim 13, wherein the first and second switch are each double-throw switches that are each coupled to ground, and wherein the current generator further comprises:

a third switch that is coupled to the negative output terminal and that is controlled by the second control signal;

a first set of resistors coupled in series with one another between the third switch and the second passive electrode of the third transistor, wherein the second input terminal of the first amplifier is coupled to a node between at least two resistors from the first set;

a fourth switch that is coupled to the positive output terminal and that is controlled by the first control signal; and

a second set of resistors coupled in series with one another between the fourth switch and the second passive electrode of the fifth transistor, wherein the second input terminal of the second amplifier is coupled to a node between at least two resistors from the second set.

15. The apparatus of claim 12, wherein the I-to-V converter further comprises a differential amplifier that outputs a differential sense voltage.

16. The apparatus of claim 12, wherein the I-to-V converter further comprises:

a current mirror that is coupled to the first passive electrode of the third transistor; and

a third amplifier having an input terminal that is coupled to the current mirror and the first passive electrode of the fifth transistor.

17. A method comprising:

actuating at least one of a first and a second low-side NMOS transistors within a class-D amplifier;

sampling voltages on each of positive and negative output terminals of the class-D amplifier when its associated low-side NMOS transistors is actuated;

generating first and second sense currents from the first and second low-side NMOS transistors of the class-D amplifier, respectively; and

converting the first and second sense currents into a sense voltage.

18. The method of claim 17, wherein the step of generating the first and second sense currents further comprises mirroring the drain-source voltages of the first and second low-side NMOS transistor on first and second sense NMOS transistors, respectively.

19. The method of claim 18, wherein the ratio of the first sense current to a first current through the first NMOS transistor is 1:

N, wherein N is greater than or equal to 1.

20. The method of claim 19, wherein the ratio of the second sense current to a second current through the second NMOS transistor is 1:

N, wherein N is greater than or equal to 1.