DYNAMIC DEVICE SWITCHING (DDS) OF AN IN-PHASE RF PA STAGE AND A QUADRATURE-PHASE RF PA STAGE

• US 20120044022A1
• Filed: 11/03/2011
• Published: 02/23/2012
• Est. Priority Date: 04/20/2010
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Jones, David E., Levesque, Chris, Southcombe, William David, Yoder, Scott, Stockert, Terry J., Walker, Gregg A.
• Granted Patent: US 8,831,544 B2
• Time in Patent Office: Days
• US Class Current: 330/296
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 2200/111 the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/537 A transformer being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H04B 2001/0416 having gain or transmission power control

Abstract

An in-phase radio frequency (RF) power amplifier (PA) stage and a quadrature-phase RF PA stage are disclosed. The in-phase RF PA stage includes a first group of arrays of amplifying transistor elements and the quadrature-phase RF PA stage includes a second group of arrays of amplifying transistor elements. A group of array bias signals is based on a selected one of a group of DDS operating modes. Each of the group of array bias signals is a current signal. The in-phase RF PA stage biases at least one of the first group of arrays of amplifying transistor elements based on the group of array bias signals. Similarly, the quadrature-phase RF PA stage biases at least one of the second group of arrays of amplifying transistor elements based on the group of array bias signals.

Claims

1. Circuitry comprising:

an in-phase radio frequency (RF) power amplifier (PA) stage comprising a first plurality of arrays of amplifying transistor elements and adapted to bias at least one of the first plurality of arrays based on a plurality of array bias signals, such that the plurality of array bias signals is based on a selected one of a plurality of dynamic device switching (DDS) operating modes; and

a quadrature-phase RF PA stage comprising a second plurality of arrays of amplifying transistor elements and adapted to bias at least one of the second plurality of arrays based on the plurality of array bias signals,

wherein each of the plurality of array bias signals is a current signal.

2. The circuitry of claim 1 wherein:

the in-phase RF PA stage is further adapted to receive and amplify an in-phase RF stage input signal to provide an in-phase RF stage output signal using at least one of the first plurality of arrays that is biased; and

the quadrature-phase RF PA stage is further adapted to receive and amplify a quadrature-phase RF stage input signal to provide a quadrature-phase RF stage output signal using at least one of the second plurality of arrays that is biased.

3. The circuitry of claim 1 further comprising control circuitry adapted to select the one of the plurality of DDS operating modes.

4. The circuitry of claim 1 wherein the first plurality of arrays of amplifying transistor elements comprises a first array of amplifying transistor elements and a second array of amplifying transistor elements.

5. The circuitry of claim 4 wherein the first array of amplifying transistor elements comprises a first alpha transistor element, a second alpha transistor element, and up to and including an N^TH alpha transistor element.

6. The circuitry of claim 5 wherein the first array of amplifying transistor elements are coupled in parallel with one another.

7. The circuitry of claim 5 wherein the second array of amplifying transistor elements comprises a first beta transistor element, a second beta transistor element, and up to and including an M^TH beta transistor element.

8. The circuitry of claim 7 wherein N may be any positive integer and M may be any positive integer.

9. The circuitry of claim 4 wherein the second plurality of arrays of amplifying transistor elements comprises a third array of amplifying transistor elements and a fourth array of amplifying transistor elements.

10. The circuitry of claim 9 wherein the third array of amplifying transistor elements comprises a first gamma transistor element, a second gamma transistor element, and up to and including a P^TH gamma transistor element.

11. The circuitry of claim 10 wherein the fourth array of amplifying transistor elements comprises a first delta transistor element, a second delta transistor element, and up to and including a Q^TH delta transistor element.

12. The circuitry of claim 1 wherein the in-phase RF PA stage is an in-phase driver PA stage.

13. The circuitry of claim 12 wherein the quadrature-phase RF PA stage is a quadrature-phase driver PA stage.

14. The circuitry of claim 1 wherein the in-phase RF PA stage is an in-phase final PA stage.

15. The circuitry of claim 14 wherein the quadrature-phase RF PA stage is a quadrature-phase final PA stage.

16. The circuitry of claim 1 further comprising:

a first RF PA comprising;

a first non-quadrature PA path having a first single-ended output; and

a first quadrature PA path, which comprises the in-phase RF PA stage and the quadrature-phase RF PA stage, and is coupled between the first non-quadrature PA path and an antenna port, such that the first quadrature PA path has a first single-ended input, which is coupled to the first single-ended output; and

a second RF PA comprising a second quadrature PA path coupled to the antenna port,

wherein the antenna port is configured to be coupled to an antenna.

17. The circuitry of claim 1 further comprising:

a first multi-mode multi-band quadrature RF PA, which comprises the in-phase RF PA stage and the quadrature-phase RF PA stage, and is coupled to multi-mode multi-band alpha switching circuitry via a single alpha PA output; and

the multi-mode multi-band alpha switching circuitry having;

a first alpha non-linear mode output associated with a first non-linear mode RF communications band; and

a plurality of alpha linear mode outputs, such that each of the plurality of alpha linear mode outputs is associated with a corresponding one of a first plurality of linear mode RF communications bands.

18. The circuitry of claim 1 further comprising:

a first RF PA comprising a first final stage, which comprises the in-phase RF PA stage and the quadrature-phase RF PA stage, and has a first final bias input, such that bias of the first final stage is via the first final bias input;

PA control circuitry;

a PA-digital communications interface (DCI) coupled between a digital communications bus and the PA control circuitry; and

a final stage current digital-to-analog converter (IDAC) coupled between the PA control circuitry and the first final bias input.

19. The circuitry of claim 1 further comprising:

a first RF PA having a first final stage, which comprises the in-phase RF PA stage and the quadrature-phase RF PA stage, and is adapted to;

receive and amplify a first RF input signal to provide a first RF output signal; and

receive a first final bias signal to bias the first final stage;

PA bias circuitry adapted to receive a bias power supply signal and provide the first final bias signal based on the bias power supply signal; and

a direct current (DC)-DC converter adapted to receive a DC power supply signal from a DC power supply and provide the bias power supply signal based on the DC power supply signal, such that a voltage of the bias power supply signal is greater than a voltage of the DC power supply signal.

20. The circuitry of claim 1 further comprising:

a direct current (DC)-DC converter comprising;

a power amplifier (PA) envelope power supply comprising a charge pump buck converter coupled to radio frequency (RF) PA circuitry; and

a PA bias power supply comprising a charge pump coupled to the RF PA circuitry; and

the RF PA circuitry comprising the in-phase RF PA stage and the quadrature-phase RF PA stage.

21. The circuitry of claim 1 further comprising:

multi-mode multi-band RF power amplification circuitry, which comprises the in-phase RF PA stage and the quadrature-phase RF PA stage, and has at least a first RF input and a plurality of RF outputs, such that;

configuration of the multi-mode multi-band RF power amplification circuitry associates one of the at least the first RF input with one of the plurality of RF outputs; and

the configuration is associated with at least a first look-up table (LUT);

PA control circuitry coupled between the multi-mode multi-band RF power amplification circuitry and a PA-digital communications interface (DCI), such that the PA control circuitry has at least the first LUT, which is associated with at least a first defined parameter set; and

the PA-DCI, which is coupled to a digital communications bus.

22. A method comprising:

providing an in-phase RF PA stage comprising a first plurality of arrays of amplifying transistor elements;

providing a quadrature-phase RF PA stage comprising a second plurality of arrays of amplifying transistor elements;

biasing at least one of the first plurality of arrays based on a plurality of array bias signals, such that the plurality of array bias signals is based on a selected one of a plurality of DDS operating modes; and

biasing at least one of the second plurality of arrays based on the plurality of array bias signals,

wherein each of the plurality of array bias signals is a current signal.