Overvoltage and Overcurrent Protection Scheme
First Claim
1. A method for protecting a transistor against overload, the method comprising:
- providing an input signal to a base terminal of a transistor for a first amount of time;
upon expiration of the first amount of time, making a determination of whether an overload condition exists at the transistor;
disabling the transistor for a second amount of time when the determination is that an overload condition exists at the transistor; and
providing the input signal to the base terminal upon expiration of the second amount of time.
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Accused Products
Abstract
Disclosed are methods and corresponding systems to detect and prevent and/or eliminate overload conditions for a transistor. According to an embodiment, a method includes providing an input signal to a base terminal of a transistor for a first amount of time, determining if an overload condition exists at the transistor, disabling the transistor for a second amount of time when the overload condition exists at the transistor, and providing the communication signal to the base terminal upon expiration of the second amount of time. Additional overload conditions can be checked upon expiration of the second amount of time as well.
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Citations
20 Claims
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1. A method for protecting a transistor against overload, the method comprising:
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providing an input signal to a base terminal of a transistor for a first amount of time; upon expiration of the first amount of time, making a determination of whether an overload condition exists at the transistor; disabling the transistor for a second amount of time when the determination is that an overload condition exists at the transistor; and providing the input signal to the base terminal upon expiration of the second amount of time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A circuit comprising:
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a first signal line coupled to a collector terminal of a transistor; an overload protection module coupled between a second signal line and a base terminal of the transistor, the overload protection module including; means for applying a signal to the base terminal of a transistor for a first amount of time, the signal representative of a signal on the second signal line; means for making a determination of whether an overload condition exists at the transistor upon expiration of the first amount of time; means for disabling the transistor for a second amount of time when the determination is that an overload condition exists at the transistor; and means for applying the signal to the base terminal upon expiration of the second amount of time. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A field programmable gate array (FPGA) having an association of logic gates, wherein the logic gates are wired to perform functions, the functions comprising:
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providing an input signal to a base terminal of a transistor for a first amount of time; upon expiration of the first amount of time, making a determination of whether an overload condition exists at the transistor; disabling the transistor for a second amount of time when the determination is that an overload condition exists at the transistor; and providing the input signal to the base terminal upon expiration of the second amount of time. - View Dependent Claims (19, 20)
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Specification