Single Device Driver Circuit to Control Three-Dimensional Memory Element Array
First Claim
1. A memory array, comprising:
- an array of memory cells positioned between a plurality of word lines and a plurality of bit lines; and
a circuit comprising;
a bleeder diode having a first terminal coupled to a first bit line of the plurality of bit lines;
a bit line bleeder diode controller having a control input lead, a source lead, and an output lead, wherein the output lead is coupled to a second terminal of the bleeder diode, the source lead is coupled to a bias voltage source, and the control input lead is coupled to a bit line decoder control lead; and
at least one first transistor of a first conductivity type having a gate coupled to the bit line decoder control lead, at least one of a source or a drain coupled to a bit line bias generator circuit, and the other one of the source or the drain coupled to the first bit line.
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Accused Products
Abstract
A memory device includes diode plus resistivity switching element memory cells coupled between bit and word lines, single device bit line drivers with gates coupled to a bit line decoder control lead, sources/drains coupled to a bit line driver, and drains/sources coupled to bit lines, single device word line drivers with gates coupled to a word line decoder control lead, sources/drains coupled to a word line driver output, and drains/sources coupled to word lines, a first bleeder diode coupled between a bit line and a first bleeder diode controller, and a second bleeder diode coupled between a word line and a second bleeder diode controller. The first bleeder diode controller connects the first bleeder diode to low voltage in response to a bit line decoder signal. The second bleeder diode controller connects the second bleeder diode to high voltage in response to a word line decoder signal.
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Citations
32 Claims
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1. A memory array, comprising:
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an array of memory cells positioned between a plurality of word lines and a plurality of bit lines; and a circuit comprising; a bleeder diode having a first terminal coupled to a first bit line of the plurality of bit lines; a bit line bleeder diode controller having a control input lead, a source lead, and an output lead, wherein the output lead is coupled to a second terminal of the bleeder diode, the source lead is coupled to a bias voltage source, and the control input lead is coupled to a bit line decoder control lead; and at least one first transistor of a first conductivity type having a gate coupled to the bit line decoder control lead, at least one of a source or a drain coupled to a bit line bias generator circuit, and the other one of the source or the drain coupled to the first bit line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory array, comprising:
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an array of memory cells positioned between a plurality of word lines and a plurality of bit lines; and a circuit comprising; a bleeder diode having a first terminal coupled to a first word line of the plurality of word lines; a word line bleeder diode controller having a control input lead, a source lead, and an output lead, wherein the output lead is coupled to a second terminal of the bleeder diode, the source lead is coupled to a bias voltage source, and the control input lead is coupled to a word line decoder control lead; and at least one first transistor of a first conductivity type having a gate coupled to the word line decoder control lead, at least one of a source or a drain coupled to a word line bias generator circuit, and the other one of the source or the drain coupled to the first word line. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A memory device, comprising:
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a bit line decoder; a bit line bias generator circuit having a plurality of outputs; a word line decoder; a word line bias generator circuit having a plurality of outputs; a plurality of bit lines; a plurality of word lines; a plurality of memory cells, each memory cell comprising a diode steering element in series with a resistivity switching storage element, each memory cell coupled between one of the plurality of bit lines and one of the plurality of word lines; a plurality of PMOS single device bit line side drivers each having a gate coupled to the same bit line decoder control lead, one of a source or drain coupled to a different one of the plurality of bit line bias generator circuit outputs (804, Selb1 to Selb16), and the other one of the source or the drain coupled to a different one of the plurality of bit lines; a plurality of NMOS single device word line side drivers each having a gate coupled to the same word line decoder control lead, one of a source or drain coupled to a different one of the plurality of word line bias generator circuit outputs, and the other one of the source or the drain coupled to a different one of the plurality of word lines; a bit line bleeder diode having a first terminal coupled to a first bit line of the plurality of bit lines; a word line bleeder diode having a first terminal coupled to a first word line of the plurality of word lines; a bit line bleeder diode controller having a control input lead, a source lead, and an output lead, wherein the output lead is coupled to a second terminal of the bleeder diode, the source lead is coupled to a bias voltage source, and the control input lead is coupled to a bit line decoder control lead; and a word line bleeder diode controller having a control input lead, a source lead, and an output lead, wherein the output lead is coupled to a second terminal of the bleeder diode, the source lead is coupled to a bias voltage source, and the control input lead is coupled to a word line decoder control lead. - View Dependent Claims (22, 23, 24, 25, 26)
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27. A method of fabricating a memory device, comprising:
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forming a plurality of memory cells, each memory cell memory cell comprising a diode steering element in series with a resistivity switching storage element; and forming a plurality of bleeder diodes each comprising a diode steering element, wherein the plurality of bleeder diodes are formed so that; a first subset of the plurality of bleeder diodes are each electrically coupled to one of a source or drain of one of a plurality of NMOS transistors, each one of the plurality of NMOS transistors having a gate coupled to a bit line decoder, and the other one of the source or drain coupled to a first voltage source, and a second subset of the plurality of bleeder diodes are each electrically coupled to one of a source or drain of a plurality of PMOS transistors, each having a gate coupled to a word line decoder, and the other one of the source drain coupled to a second voltage source. - View Dependent Claims (28, 29, 30, 31)
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32. A memory device comprising:
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means for biasing bit lines controlled by signals from a bit line decoder used to select one or more bit lines; and means for biasing word lines controlled by signals from a word line decoder used to select one or more word lines.
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Specification