High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization

• US 20120044984A1
• Filed: 10/28/2011
• Published: 02/23/2012
• Est. Priority Date: 01/20/2005
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared L., Ho, Andrew, Farjad-Rad, Ramin, Poulton, John W., Donnelly, Kevin S., Leibowitz, Brian, Chen, Fred F.
• Granted Patent: US 9,148,322 B2
• Time in Patent Office: Days
• US Class Current: 375/233
• CPC Class Codes: H04L 1/0026 Transmission of channel quality indication
• CPC Class Codes: H04L 2025/03503 as a combination of feedback and prediction filters
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 25/497 by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 27/01 Equalisers baseband equalizers at the transmitter end H04L25/03343; in analogue transmission systems H04B3/04, H04B7/005
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
• CPC Class Codes: H04W 52/20 using error rate
• CPC Class Codes: H04W 52/225 Calculation of statistics, e.g. average, variance
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

Claims

1. A system comprising:

a transmitter having circuitry to equalize data to be transmitted over a signaling path; and

a receiver to receive the data, the receiver having

a linear equalizer to equalize the data received from the signaling path, and

a decision-feedback equalizer with one or more taps to equalize an output of the linear equalizer, and

where the circuitry is to equalize the data to be transmitted to the receiver only for pre-tap interference.

2. The system of claim 1, where at least one tap of the decision-feedback equalizer includes a partial-response tap.

3. The system of claim 1, where:

the circuitry includes a main tap and a second tap with a symbol latency relative to the main tap; and

the circuitry supports

a first mode in which the symbol latency of the second tap is set to a first symbol latency relative to the main tap; and

a second mode in which the symbol latency of the second tap is set to a second symbol latency relative to the main tap.

4. The system of claim 3, where the second tap precedes the main tap in the first mode and follows the main tap in the second mode.

5. The system of claim 4, where the linear equalizer is enabled in the first mode and is disabled in one of the second mode or a third mode.

6. The system of claim 5, where the transmitter is to receive from the receiver a measure of signal quality, and is to automatically select the first or the second mode in response to the measure of signal quality.

7. The system of claim 6, where the measure of signal quality includes a least one of a data level, a voltage margin or a bit error rate associated with the data transmitted by the transmitter to the receiver.

8. The system of claim 7, where the circuitry includes compensation for pre-tap latency that is enabled in the first mode and is disabled in at least one of the second mode or a third mode.

9. The system of claim 1, where the transmitter transmits the data to the receiver as a serial, differential output signal.

10. The system of claim 1, where the circuitry includes plural subdrivers each contributing to overall drive strength used for the data in a manner varied in accordance with a multi-bit power setting.

11. The system of claim 10, where total drive current provided by all sub-drivers remains constant irrespective of variance of drive current for any individual subdriver.

12. The system of claim 10, where drive current of each of the plural subdrivers is varied according to a fraction of ½

ⁿ.

13. The system of claim 1, where the transmitter further comprises a serializer to accept parallel data and produce an input bit sequence, where the transmitter uses the circuitry to transmit the data responsive to the input bit sequence as a serial output signal.

14. A system comprising:

a transmitter having circuitry to equalize data to be transmitted over a signaling path; and

a receiver to receive the data, the receiver having

a linear equalizer to equalize the data received from the signaling path, and

a decision-feedback equalizer with one or more taps to equalize an output of the linear equalizer;

where the decision-feedback equalizer is to equalize the output of the linear equalizer for symbols of latency greater than a predetermined latency, and where the circuitry is to equalize the data for symbol latency not overlapping equalization provided by the decision-feedback equalizer.

15. The system of claim 14, where the decision-feedback equalizer is to equalize the output of the linear equalizer only for post cursor interference, and where the circuitry of the transmitter is to equalize the data only for precursor interference.

16. The system of claim 14, where at least one tap of the decision-feedback equalizer includes a partial-response tap.

17. The system of claim 14, where:

the circuitry includes a main tap and a second tap with a symbol latency relative to the main tap; and

the circuitry supports;

a first mode in which the symbol latency of the second tap is set to a first symbol latency relative to the main tap, and

a second mode in which the symbol latency of the second tap is set to a second symbol latency relative to the main tap.

18. The system of claim 17, where in the first mode, the second tap is to provide equalization only for precursor interference, and where in the second mode, the second tap is to provide equalization only for post-cursor interference.

19. The system of claim 14, where the circuitry includes a tap to compensate for pre-cursor interference, where the tap is enabled in the first mode and is disabled in at least one of the second mode or a third mode.

20. The system of claim 14 where the transmitter transmits the data to the receiver as a serial, differential output signal.

21. The system of claim 14 where the circuitry includes plural subdrivers, each contributing to overall drive strength used for the data in a manner varied in accordance with a multi-bit power setting.

22. The system of claim 21, where total drive current provided by all sub-drivers remains constant irrespective of variance of drive current for any individual subdriver.

23. The system of claim 22, where drive current of each of the plural subdrivers is varied according to a fraction of ½

ⁿ.

24. The system of claim 14, where the transmitter further comprises a serializer to accept parallel data and produce an input bit sequence, where the transmitter uses the circuitry to transmit the data responsive to the input bit sequence as a serial output signal.

25. The system of claim 14, where the decision-feedback equalizer is to equalize the first receiver-equalized signal for interference for symbol latency exceeding a first latency relative to a current symbol, and where the circuitry on the first integrated circuit is to equalize the input data signal for interference associated with symbol latency not exceeding the current latency relative to the current symbol.

26. A method comprising:

using circuitry on a first integrated circuit to equalize an input data signal and transmit an equalized data signal to a second integrated circuit;

using a linear equalizer on the second integrated circuit to further equalize the equalized data signal to provide a first receiver-equalized signal; and

using a decision-feedback equalizer on the second integrated circuit for further equalize the first receiver-equalized signal to provide a second receiver-equalized signal;

where using the decision-feedback equalizer includes equalizing the first receiver-equalized signal for symbol latency exceeding a first latency relative to a current symbol, and where using the circuitry on the first integrated circuit includes equalizing the input data signal for symbol latency not exceeding the first latency relative to the current symbol.

27. The method of claim 26, where using the decision-feedback equalizer includes equalizing the first receiver-equalized signal only for post-cursor interference and using the circuitry includes equalizing the input data signal only for precursor interference.

28. The method of claim 26, where using the circuitry includes:

in a first mode, using at least one tap to equalize the input data signal for precursor intersymbol interference; and

in a second mode, using the at least one tap to equalize the input data signal for post-cursor intersymbol interference.

29. The method of claim 28, where using the decision-feedback equalizer includes disabling at least one decision-feedback equalizer tap in the second mode.

30. The method of claim 29, where in the first mode the at least one decision-feedback equalizer tap is to equalize the first receiver-equalized signal for the post-cursor interference.

31. A method comprising:

using circuitry on a first integrated circuit to equalize an input data signal and transmit an equalized data signal to a second integrated circuit;

using a linear equalizer on the second integrated circuit to further equalize the equalized data signal to provide a first receiver-equalized signal; and

using a decision-feedback equalizer on the second integrated circuit for further equalize the first receiver-equalized signal to provide a second receiver-equalized signal;

where using the decision-feedback equalizer includes equalizing the first receiver-equalized signal for symbol latency exceeding a first latency relative to a current symbol, and where using the circuitry on the first integrated circuit includes equalizing the input data signal for symbol latency not overlapping the decision-feedback equalizer.