Combining Write Buffer with Dynamically Adjustable Flush Metrics

• US 20120047332A1
• Filed: 08/20/2010
• Published: 02/23/2012
• Est. Priority Date: 08/20/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Bannon, Peter J., Beaumont-Smith, Andrew J., Gunna, Ramesh, Lien, Wei-han, Lilly, Brian P., Yeh, Tse-Yu, Patwardhan, Jaidev P., Wen, Shih-Chieh R.
• Granted Patent: US 8,352,685 B2
• Time in Patent Office: Days
• US Class Current: 711/135
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/127 using additional replacement algorithms
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/502 using adaptive policy

Abstract

In an embodiment, a combining write buffer is configured to maintain one or more flush metrics to determine when to transmit write operations from buffer entries. The combining write buffer may be configured to dynamically modify the flush metrics in response to activity in the write buffer, modifying the conditions under which write operations are transmitted from the write buffer to the next lower level of memory. For example, in one implementation, the flush metrics may include categorizing write buffer entries as “collapsed.” A collapsed write buffer entry, and the collapsed write operations therein, may include at least one write operation that has overwritten data that was written by a previous write operation in the buffer entry. In another implementation, the combining write buffer may maintain the threshold of buffer fullness as a flush metric and may adjust it over time based on the actual buffer fullness.

Claims

1. An apparatus comprising:

a cache;

a write buffer coupled to the cache and configured to buffer write operations that access the cache, wherein the write buffer comprises a plurality of entries, each entry configured to combine write operations on a cache block granularity; and

a control circuit coupled to the write buffer, wherein the control circuit is configured to cause the write buffer to transmit one or more combined write operations from one or more entries of the plurality of entries to a next level of memory below the cache responsive to one or more flush metrics applied by the control circuit and responsive to a fullness of the write buffer, and wherein the control circuit is configured to dynamically modify the one or more flush metrics responsive to activity in the write buffer, wherein dynamically modifying the one or more flush metrics changes a frequency of transmission of combined write operations from the write buffer to the next level of memory.

2. The apparatus as recited in claim 1 wherein the one or more flush metrics comprise a collapse state in each entry of the plurality of entries, wherein the collapse state indicates whether or not at least one collapsed write has been detected in the write operations combined in that entry, and wherein the control circuit is configured to cause the transmission of the one or more combined write operations responsive to the number of occupied buffer entries that are not in the collapsed state reaching the threshold.

3. The apparatus as recited in claim 2 further wherein the control circuit is further configured to detect the collapsed write to a first entry, and to modify a first collapse state of the first entry to indicate collapsed.

4. The apparatus as recited in claim 3 further comprising an age counter corresponding to each entry of the plurality of entries, wherein the control circuit is configured to modify the collapsed state in a second entry of the plurality of entries to indicate not collapsed in response to the age counter reaching a second threshold, and wherein the control circuit is configured to reset the age counter is response to a write operation hitting in the second entry.

5. The apparatus as recited in claim 1 wherein the one or more flush metrics comprise a threshold of fullness of the write buffer, wherein the control circuit is configured to cause the one or more combined write operations to be transmitted responsive to a number of occupied entries in the write buffer reaching the threshold of fullness, and wherein the control circuit is configured to decrease the threshold responsive to detecting a buffer full event.

6. The apparatus as recited in claim 5 wherein the control circuit is configured to increase the threshold responsive to a predefined number of write operations being received without an occurrence of the buffer full event.

7. A method comprising:

a control circuit monitoring activity in a write buffer;

responsive to the activity, the control circuit modifying one or more flush metrics maintained by the control circuit; and

the control circuit causing one or more write operations from at least one buffer entry in the write buffer responsive to the one or more flush metrics and a fullness of the write buffer.

8. The method as recited in claim 7 wherein the monitoring comprises detecting a first write operation that hits in a first entry of the write buffer and that updates at least one byte that is already updated in the first entry, and wherein the one or more flush metrics comprise a state in each entry, and wherein the modifying comprises setting a state in the first entry indicating the detecting.

9. The method as recited in claim 8 further comprising comparing a number of write buffer entries that are storing write operations to a fullness threshold, wherein the first entry is excluded from the number.

10. The method as recited in claim 7 wherein the activity comprises a first number of consecutive write operations without filling the write buffer, and wherein the one or more flush metrics comprise a fullness threshold, and wherein the modifying comprises increasing the fullness threshold.

11. The method as recited in claim 10 wherein the activity comprises a buffer full event, and wherein the modifying comprises decreasing the fullness threshold.

12. An apparatus comprising:

a cache;

a write buffer coupled to the cache and configured to buffer write operations that update the cache subsequent to the write operations updating the cache, wherein the write buffer is configured to merge a plurality of write operations that update data in a same cache block; and

a control circuit coupled to the write buffer, wherein the write buffer control circuit is configured to cause the write buffer to transmit one or more merged write operations from the write buffer to a next level of memory responsive to the write buffer approaching a full state, and wherein the control circuit is configured to detect a first write operation received from the cache that hits in a first write buffer entry of the write buffer and that updates at least one byte updated by a previous write operation represented in the first write buffer entry, wherein the control circuit is configured to remove the first write buffer entry from consideration in determining if the write buffer is approaching a full state.

13. The apparatus as recited in claim 12 wherein the control circuit is configured to determine that the write buffer is approaching a full state responsive to a fullness threshold, wherein the first write buffer entry is not counted toward reaching the threshold.

14. The apparatus as recited in claim 12 wherein the control circuit is configured to record a state in the first write buffer entry indicating that the first write operation has been detected.

15. The apparatus as recited in claim 14 wherein the first write buffer entry further includes an age indication, and wherein the control circuit is configured to change the state to indicate that no write operation is detected that updates at least one byte updated by the previous write operation, wherein the control circuit is configured to change the state responsive to the age indication reaching a first age threshold subsequent to detecting the first write operation.

16. The apparatus as recited in claim 15 wherein the control circuit is configured to reset the age indication responsive to detecting a second write operation which hits in the first write buffer entry subsequent to the first write operation.

17. The apparatus as recited in claim 14 wherein the write buffer control circuit is further configured to cause the write buffer to transmit write operations from the write buffer to the next level of memory responsive to the age indication reaching a second age threshold that is higher than the first age threshold.

18. An apparatus comprising:

a write buffer configured to accumulate writes to a plurality of cache blocks prior to writing a cache;

a circuit configured to monitor the write buffer and to adjust a threshold value that determines when an accumulated write is selected from the store buffer and written to the cache, wherein the circuit is configured to adjust the threshold value dependent on a frequency at which the write buffer becomes full and dependent on a number of writes that occur without the write buffer becoming full.

19. The apparatus as recited in claim 18 wherein the circuit is further configured to increase the threshold value responsive to detecting a first number of consecutive write operations without a buffer full event.

20. The apparatus as recited in claim 19 wherein the circuit is configured to detect the first number responsive to a count of consecutive write operations, wherein the circuit is configured to reset the count responsive to the buffer full event.

21. The apparatus as recited in claim 18 wherein the circuit is further configured to decrease the threshold value responsive to detecting a buffer full event.

22. An apparatus comprising:

a processor core configured to execute a store operation and to generate a write operation responsive to the store operation;

a write-through cache coupled to receive the write operation and configured to update a cache block in the cache with write data corresponding to the write data responsive to detecting hit in the write through cache for the write operation;

a combining write buffer configured to accumulate write operations from the write through cache, wherein the combining write buffer is configured to combine write operations within a cache block into one entry in the combining write buffer, and wherein the combining write buffer is configured to dynamically modify one or more flush metrics responsive to activity in the combining write buffer, wherein the combining write buffer is configured to determine when to transmit one or more combined write operations in response to the one or more flush metrics; and

a second level cache coupled to receive the combined write operations from the combining write buffer and configured to update cache blocks stored therein with the combined write operations.

23. The apparatus as recited in claim 22 wherein the one or more flush metrics comprise a collapsed state in each entry indicating that at least one write operation has been detected which overwrites at least one byte that is updated by a previous write operation in the entry.

24. The apparatus as recited in claim 22 wherein the one or more flush metrics comprise a full threshold, and wherein the full threshold is increased in response to detecting a first number of consecutive write operations without a buffer full event, and wherein the full threshold is decreased in response to detecting the buffer full event.