SECURE FIELD-PROGRAMMABLE GATE ARRAY (FPGA) ARCHITECTURE

• US 20120047371A1
• Filed: 08/23/2010
• Published: 02/23/2012
• Est. Priority Date: 08/23/2010
• Status: Active Grant

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Woodall, Thomas R.
• Granted Patent: US 8,516,268 B2
• Time in Patent Office: Days
• US Class Current: 713/189
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method and system for configuring a field-programmable gate array (FPGA) includes receiving an encrypted FPGA load-decryption key at an FPGA from a remote key-storage device. The remote key-storage device may be external to and operatively connected with the FPGA. The encrypted FPGA load-decryption key is decrypted using a session key, which may be stored at both the FPGA and the remote key-storage device. Encrypted FPGA-configuration data is received at the FPGA, and decrypted and authenticated using the decrypted FPGA load-decryption key. The decryption of the FPGA-configuration data may indicate a cryptographic state associated with the FPGA-configuration data, which may be used in recurring authentication of the FPGA-configuration data. For recurring authentication, a challenge message may be received at the FPGA from an authentication device, which may be encrypted using the cryptographic state and the session key to generate a response message. The response message may then be sent to the authentication device to determine authenticity of the FPGA-configuration data.

Claims

1. A method of configuring a field-programmable gate array (FPGA), the method comprising:

receiving, at an FPGA, an encrypted FPGA load-decryption key from a remote key-storage device, wherein the remote key-storage device is external to and operatively connected with the FPGA;

decrypting the encrypted FPGA load-decryption key in a key-security unit to provide a decrypted FPGA load-decryption key;

receiving encrypted FPGA-configuration data at the FPGA; and

decrypting and authenticating, in a configuration-data security unit, the FPGA-configuration data using the decrypted FPGA load-decryption key.

2. The method of claim 1, wherein the FPGA-configuration data is decrypted using an advanced encryption standard counter with cipher-block chaining-message authentication code (AES-CCM) encryption mode.

3. The method of claim 1, wherein the encrypted FPGA-configuration data is received from a memory device including a programmable read-only memory (PROM) device.

4. The method of claim 1, wherein the step of decrypting and authenticating the FPGA-configuration data is non-bypassable for configuring the FPGA.

5. The method of claim 1, wherein decrypting the FPGA-configuration data indicates a cryptographic state associated with the FPGA-configuration data, the method further comprising:

receiving a challenge message at the FPGA from an authentication device, wherein the authentication device is external to and operatively connected with the FPGA;

encrypting the challenge message in a state-encryption unit using the cryptographic state to generate a response message; and

sending the response message to the authentication device, wherein the authentication device decrypts the response message to generate a decrypted challenge message, and compares the challenge message with the decrypted challenge message to indicate an authenticity of the FPGA-configuration data.

6. The method of claim 5, wherein the challenge message is encrypted using an advanced encryption standard cipher-block chaining (AES-CBC) encryption mode.

7. The method of claim 5, wherein the cryptographic state is determined based on at least a part of the FPGA-configuration data.

8. The method of claim 5, wherein the encrypted FPGA load-decryption key is decrypted using a session key, wherein the common key is stored both in the FPGA and in the remote key-storage device.

9. The method of claim 8, wherein the encryption of the challenge message is performed using the session key, wherein the session key is further stored in the authentication device.

10. The method of claim 8, wherein the session key is calculated at the FPGA and the remote key-storage device using a key-agreement protocol.

11. The method of claim 10, wherein the key-agreement protocol comprises one of a Menezes-Qu-Vanstone (MQV) protocol, an Elliptic-curve MQV (EC-MQV) protocol, and a Diffie-Hellman protocol.

27. An article of manufacture comprising a tangible computer-readable medium that contains computer instructions therein which, when executed by a processor, carries out the method of claim 2.

12. A system for configuring a field-programmable gate array (FPGA), the system comprising:

a key interface that receives an encrypted FPGA load-decryption key at an FPGA from a remote key-storage device, wherein the remote key-storage device is external to and operatively connected with the FPGA;

a key-security unit that decrypts the encrypted FPGA load-decryption key to provide a decrypted FPGA load-decryption key;

a load interface that receives encrypted FPGA-configuration data at the FPGA; and

a configuration-data security unit that decrypts and authenticates the FPGA-configuration data using the decrypted FPGA load-decryption key.

13. The system of claim 12, wherein the configuration-data security unit decrypts the FPGA-configuration data using an advanced encryption standard counter with cipher-block chaining-message authentication code (AES-CCM) encryption mode.

14. The system of claim 12, wherein the encrypted FPGA-configuration data is received at the load interface from a memory device comprising a programmable read-only memory (PROM) device.

15. The system of claim 12, wherein at least one of the key-security unit, the configuration-data security unit and the state-encryption unit is internal to the FPGA.

16. The system of claim 12, wherein the configuration-data security unit is non-bypassable for configuring the FPGA.

17. The system of claim 12, wherein the configuration-data security unit generates a cryptographic state associated with the FPGA-configuration data, the system further comprising:

an authentication input interface that receives a challenge message at the FPGA from an authentication device, wherein the authentication device is external to and operatively connected with the FPGA;

a state-encryption unit that encrypts the challenge message using the cryptographic state to generate a response message; and

an authentication output interface that sends the response message to the authentication device, wherein the authentication device decrypts the response message to generate a decrypted challenge message, and compares the challenge message with the decrypted challenge message to indicate an authenticity of the FPGA-configuration data.

18. The system of claim 16, wherein the state-encryption unit encrypts the challenge message using an advanced encryption standard cipher-block chaining (AES-CBC) encryption mode.

19. The system of claim 17, wherein the cryptographic state is determined based on at least a part of the FPGA-configuration data.

20. The system of claim 17, wherein the key-security unit uses a session key for decrypting the FPGA load-decryption key, wherein the common key is stored both in the FPGA and in the remote key-storage device.

21. The system of claim 20, wherein the state-encryption unit uses the session key for encrypting the challenge message, wherein the session key is further stored in the authentication device.

22. The system of claim 20, wherein the session key is calculated at the FPGA and the remote key-storage device using a key-agreement protocol.

23. The system of claim 22, wherein the key-agreement protocol comprises one of a Menezes-Qu-Vanstone (MQV) protocol, an Elliptic-curve MQV (EC-MQV) protocol, and a Diffie-Hellman protocol.

24. The system of claim 22, wherein the remote key-storage device includes a secure processor, wherein the secure processor is configured to use the key-agreement protocol and to facilitate the generation of the session key as an output of the remote key-storage device.

25. A system for configuring a field-programmable gate array (FPGA), the system comprising:

a load interface that receives encrypted FPGA-configuration data at the FPGA;

a configuration-data security unit that decrypts and authenticates the FPGA-configuration data using a FPGA load-decryption key, wherein the configuration-data security unit generates a cryptographic state associated with the FPGA-configuration data;

an authentication input interface that receives a challenge message at the FPGA from an authentication device, wherein the authentication device is external to and operatively connected with the FPGA;

a state-encryption unit that encrypts the challenge message using the cryptographic state to generate a response message; and

an authentication output interface for sending the response message to the authentication device, wherein the authentication device decrypts the response message to generate a decrypted challenge message, and compares the challenge message with the decrypted challenge message to indicate an authenticity of the FPGA-configuration data.

26. The system of claim 25, further comprising a programmable logic circuit programmed using the FPGA-configuration data.