Adjustable Byte Lane Offset For Memory Module to Reduce Skew

• US 20120047388A1
• Filed: 10/26/2011
• Published: 02/23/2012
• Est. Priority Date: 05/09/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Johnson, Christopher S.
• Granted Patent: US 8,631,267 B2
• Time in Patent Office: Days
• US Class Current: 713/401
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for such skew, an on-chip delay is added to the data out paths of those bits in the byte lane with otherwise would arrive early to their destinations. Such on-chip delay is provided delay circuits preferably positioned directly before the output buffers/bond pads of the integrated circuit or module. By intentionally delaying some of the outputs from the integrated circuit or module, external skew is compensated for so that all data in the byte lane arrives at the destination at substantially the same time. In a preferred embodiment, the delay circuits are programmable to allow the integrated circuit or module to be freely tailored to environments having different skew considerations, such as different styles of connectors.

Claims

1. A system, comprising:

a plurality of data paths configured for providing data signals in parallel to a plurality of first circuits, the first circuits imposing different delays to the data signals at outputs of the first circuits;

at least one delay circuit in at least one of the data paths, wherein the at least one delay circuit imposes a delay to the data signal in its data path, whereby the delay synchronizes the data signals at the outputs of the first circuit.

2. The system of claim 1, further comprising an integrated circuit, wherein the plurality of data paths are internal to the integrated circuit.

3. The system of claim 2, wherein the plurality of first circuits are also internal to the integrated circuit.

4. The system of claim 1, further comprising a plurality of integrated circuits, wherein at least one of the plurality of data paths is internal to each of the integrated circuits.

5. The system of claim 4, wherein at least one of the plurality of first circuits is also internal to each of the integrated circuits.

6. The system of claim 4, wherein the plurality of integrated circuits are mounted to a circuit board.

7. The system of claim 1, wherein the first circuits comprise a connector.

8. The system of claim 1, wherein the first circuits impose different delays to the data signals by virtue of different conductor lengths of the first circuits.

9. The system of claim 1, wherein the delay imposed by the at least one delay circuit is programmable.

10. The system of claim 1, wherein the delay imposed by the at least one delay circuit is one-time programmable.

11. The system of claim 1, wherein the delay circuits are programmable to impose different delays.

12. The system of claim 1, wherein the delay circuit is in each of the data paths.

13. The system of claim 12, wherein the delay circuit is not programmed to impose a delay in at least one of the data paths.

14. The system of claim 1, wherein the data paths comprise output data paths of an integrated circuit.

15. A system, comprising:

a plurality of data paths comprising at least one first data path and at least one second data path, the data paths for providing data signals in parallel;

a plurality of connecting circuits each for receiving one of the data signals, the connecting circuits comprising at least one first connecting circuit for receiving the data signal from the at least one first data path, and at least one second connecting circuit for receiving the data signal from the at least one second data path, wherein the at least one second connecting circuit imposes a delay to its associated data signal en route to a receiving circuit when compared to the at least one first connecting circuit;

a delay circuit at least in each of the at least one first data paths, wherein the at least one delay circuit imposes a delay to the data signal in the at least one first data path, whereby the data signals are provided synchronously in parallel to the receiving circuit.

16. The system of claim 15, further comprising an integrated circuit, wherein the plurality of data paths are internal to the integrated circuit.

17. The system of claim 16, wherein the plurality of connecting circuits are also internal to the integrated circuit.

18. The system of claim 17, wherein the receiving circuit is also internal to the integrated circuit.

19. The system of claim 15, further comprising a plurality of integrated circuits, wherein at least one of the plurality of data paths is internal to each of the integrated circuits.

20. The system of claim 19, wherein at least one of the plurality of connecting circuits is also internal to each of the integrated circuits.

21. The system of claim 19, wherein the plurality of integrated circuits are mounted to a circuit board.

22. The system of claim 15, wherein the connecting circuits comprise a connector for coupling the plurality of data paths to the receiving circuit.

23. The system of claim 15, wherein the at least one second connecting circuit imposes the delay by virtue of the at least one second connecting circuit having a longer conductor than a conductor in the at least one first connecting circuit.

24. The system of claim 15, wherein the at least one second connecting circuit imposes the delay by virtue of a device.

25. The system of claim 15, wherein the delay imposed by the delay circuit at least in each of the at least one second data paths is programmable.

26. The system of claim 15, wherein the delay imposed by the delay circuit at least in each of the at least one second data paths is one-time programmable.

27. The system of claim 15, wherein the delay circuits are programmable to impose different delays.

28. The system of claim 15, wherein the delay circuit is in each of the at least one first data path and the at least one second data path.

29. The system of claim 28, wherein the delay circuit is not programmed to impose a delay in the at least one first data path.

30. The system of claim 15, wherein the data signals comprise a byte of data, and wherein the first data paths comprise a nibble of data, and wherein the second data paths comprise a nibble of data.

31. The system of claim 15, wherein the data paths comprise output data paths of an integrated circuit.

32. A method for providing parallel data signals from a plurality of data paths to a receiving circuit, at least some of the plurality of data paths having an adjustable delay circuit, each data path configured to be coupled to the receiving circuit by a plurality of connecting circuits, wherein the connecting circuits are not uniform in the delays they impart to the parallel data signals, comprising:

receiving a request from the receiving circuit for parallel data signals from the data paths; and

adjusting the delay of at least some of the adjustable delays circuits to compensate for the delays imparted by the connecting circuits;

providing the parallel data signals to the receiving device through the connecting circuits, whereby the parallel data signals are configured to synchronously arrive at the receiving device.

33. The method of claim 32, wherein all of the data paths comprise a delay circuit, but wherein only certain delay circuits are active to result in delaying some, but not all, of the data signals.

34. The method of claim 32, wherein the plurality of data paths are internal to an integrated circuit.

35. The method of claim 32, wherein at the plurality of data paths are internal to a plurality of the integrated circuits.

36. The method of claim 35, wherein the plurality of integrated circuits are mounted to a circuit board.

37. The method of claim 32, wherein the connecting circuits comprise a connector for coupling the plurality of data paths to the receiving device.

38. The method of claim 32, wherein the receiving device comprises a mother board.

39. The method of claim 32, wherein the receiving device comprises a microprocessor.

40. The method of claim 32, wherein the connecting circuits are not uniform in the delays they impart to the parallel data signals by virtue of the connecting circuits having different conductor lengths.

41. The method of claim 32, wherein the adjustable delay circuits are one-time programmable.

42. The method of claim 32, wherein the delay circuit is in each of the data paths.

43. The method of claim 42, wherein the delay circuit is not adjusted to impose a delay in the at least one first data path.

44. The method of claim 32, wherein the data paths comprise output data paths of an integrated circuit.

45. The method of claim 32, wherein the adjusting the delay step occurs before the receiving the request step.