ARRAY SUBSTRATE

• US 20120049198A1
• Filed: 11/28/2010
• Published: 03/01/2012
• Est. Priority Date: 08/26/2010
• Status: Abandoned Application

• Current Assignee: Chunghwa Picture Tubes Limited
• Original Assignee: Chunghwa Picture Tubes Limited
• Inventors: Chang, Hsi-Ming
• Application Number:
  US12/954,901
• Publication Number:
  US 20120049198A1
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement

Abstract

An array substrate includes a substrate, an organic layer, a via hole, an inorganic layer, and a patterned transparent pixel electrode layer. The thin film transistor is disposed on the substrate, and the thin film transistor comprises a drain electrode. The organic material layer covers the substrate and the thin film transistor. The via hole penetrates the organic material layer and exposes the drain electrode. The inorganic material layer covers at least a sidewall of the via hole and a part of the organic material layer, and exposes the drain electrode through the via hole. The patterned transparent pixel electrode layer is disposed on the first inorganic material layer and in the via hole, and the patterned transparent pixel electrode layer contacts the drain electrode.

Claims

1. An array substrate, comprising:

a substrate, wherein a thin film transistor is disposed on the substrate, and the thin film transistor comprises a gate electrode, a gate insulating layer, a source electrode, and a drain electrode;

an organic material layer, covering the substrate and the thin film transistor;

a via hole, penetrating the organic material layer and exposing the drain electrode;

a first inorganic material layer, covering at least a sidewall of the via hole and a part of the organic material layer, and exposing the drain electrode; and

a patterned transparent pixel electrode layer, disposed on the first inorganic material layer and in the via hole, and contacting the drain electrode.

2. The array substrate in claim 1, wherein the patterned transparent pixel electrode layer comprises at least two main pixel electrodes and a bridge electrode, the bridge electrode is disposed between the two main pixel electrodes and connected to the two main pixel electrodes, and a width of the bridge electrode is smaller than a width of one of the two main pixel electrodes.

3. The array substrate in claim 1, wherein the first inorganic material layer is disposed only on the sidewall of the via hole, on the organic material layer around the via hole, and on the organic material layer under the bridge electrode.

4. The array substrate in claim 1, wherein the first inorganic material layer is disposed on the sidewall of the via hole and the first inorganic material layer entirely covers an upper surface of the organic material layer.

5. The array substrate in claim 1, further comprising:

a second inorganic material layer disposed between the gate insulating layer and the organic material layer, wherein the second inorganic material layer exposes a part of the drain electrode.

6. The array substrate in claim 5, wherein the second inorganic material layer is silicon nitride.

7. The array substrate in claim 1, wherein the organic material layer is an organic photo resist.

8. The array substrate in claim 1, wherein the first inorganic material layer is silicon nitride.