SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• US 20120049202A1
• Filed: 04/05/2010
• Published: 03/01/2012
• Est. Priority Date: 04/13/2009
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki
• Granted Patent: US 8,735,906 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The semiconductor device according to the present invention includes a semiconductor layer of a first conductivity type made of SiC, a body region of a second conductivity type formed on a surface layer portion of the semiconductor layer, a gate trench dug down from a surface of the semiconductor layer with a bottom surface formed on a portion of the semiconductor layer under the body region, source regions of the first conductivity type formed on a surface layer portion of the body region adjacently to side surfaces of the gate trench, a gate insulating film formed on the bottom surface and the side surfaces of the gate trench so that the thickness of a portion on the bottom surface is greater than the thickness of portions on the side surfaces, a gate electrode embedded in the gate trench through the gate insulating film, and an implantation layer formed on a portion of the semiconductor layer extending from the bottom surface of the gate trench to an intermediate portion of the semiconductor layer in the thickness direction by implantation of a second conductivity type impurity.

Claims

1. A semiconductor device comprising:

a semiconductor layer of a first conductivity type made of SiC;

a body region of a second conductivity type formed on a surface layer portion of the semiconductor layer;

a gate trench dug down from a surface of the semiconductor layer with a bottom surface formed on a portion of the semiconductor layer under the body region;

source regions of the first conductivity type formed on a surface layer portion of the body region adjacently to side surfaces of the gate trench;

a gate insulating film formed on the bottom surface and the side surfaces of the gate trench so that the thickness of a portion on the bottom surface is greater than the thickness of portions on the side surfaces;

a gate electrode embedded in the gate trench through the gate insulating film; and

an implantation layer formed on a portion of the semiconductor layer extending from the bottom surface of the gate trench to an intermediate portion of the semiconductor layer in the thickness direction by implantation of a second conductivity type impurity.

2. The semiconductor device according to claim 1, wherein

the implantation layer is an active layer provided with conductivity by activation of the second conductivity type impurity.

3. The semiconductor device according to claim 1, wherein

the implantation layer is an insulating layer maintaining an inactive state of the second conductivity type impurity after the implantation.

4. The semiconductor device according to claim 1, wherein

the thickness T₁ of portions adjacent to the source regions is not less than the thickness T₂ of remaining portions in the gate insulating film on the side surfaces of the gate trench.

5. The semiconductor device according to claim 4, wherein

the ratio (T₁/T₂) of the thickness T₁ of the portions adjacent to the source regions to the thickness T₂ of the remaining portions of the gate insulating film is 1 to 3.

6. The semiconductor device according to claim 4, wherein

the portions of the gate insulating film adjacent to the source regions protrude on both of the inner side and the outer side of the gate trench with respect to the side surfaces of the gate trench.

7. The semiconductor device according to claim 4, wherein

the ratio (T₃/T₂) of the thickness T₃ of the gate insulating film on the bottom surface of the gate trench to the thickness T₂ of the remaining portions of the gate insulating film is 1 to 2.

8. The semiconductor device according to claim 1, wherein

the surface of the semiconductor layer is an Si plane.

9. The semiconductor device according to claim 1, wherein

the bottom surface of the gate trench includes inclined portions formed on both end portions of the side surfaces of the gate trench opposed to each other in the opposed direction and inclined from the respective lower ends of the side surfaces toward the surface of the semiconductor layer, and a parallel portion connecting lower ends of the inclined portions with each other and parallel to the surface of the semiconductor layer.

10. The semiconductor device according to claim 9, wherein

the implantation layer is formed in contact with the whole area of the parallel portion.

11. The semiconductor device according to claim 1, wherein

the bottom surface of the gate trench is provided in the form of an arc in sectional view having bent surfaces bent toward the semiconductor layer on both end portions of the side surfaces of the gate trench opposed to each other in the opposed direction.

12. The semiconductor device according to claim 1, wherein

the depth of the implantation layer is 0.1 μ

m to 0.5 μ

m.

13. The semiconductor device according to claim 1, wherein

the second conductivity type impurity concentration in the implantation layer is 1×

10¹⁶ cm<sup>−

3</sup> to 1×

10²¹ cm<sup>−

3</sup>.

14. A method of manufacturing a semiconductor device, comprising the steps of:

forming a second conductivity type region on a surface layer portion of a semiconductor layer of a first conductivity type made of SiC by implanting a second conductivity type impurity from a surface of the semiconductor layer;

forming a first conductivity type region on a surface layer portion of the second conductivity type region by implanting a first conductivity type impurity from a surface of the second conductivity type region;

forming a body region and a source region by activating the second conductivity type region and the first conductivity type region by a heat treatment;

forming a gate trench dug down from the surface in the semiconductor layer;

covering side surfaces of the gate trench with a mask;

forming an implantation layer on a portion extending from a bottom surface of the gate trench to an intermediate portion of the semiconductor layer in the thickness direction by implanting a second conductivity type impurity from the bottom surface of the gate trench into the semiconductor layer after the formation of the mask;

forming a gate insulating film on the bottom surface and the side surfaces by removing the mask and oxidizing the bottom surface and the side surfaces of the gate trench after the formation of the implantation layer; and

forming a gate electrode on the gate insulating film to fill up the gate trench.

15. The method of manufacturing a semiconductor device according to claim 14, wherein

the step of forming the gate trench includes the steps of forming a first mask on the surface of the semiconductor layer and etching the semiconductor layer through the first mask, and

the step of covering the side surfaces with the mask includes the steps of forming a second mask made of a different material from the first mask on the bottom surface and the side surfaces as well as on the first mask and removing a portion of the second mask on the bottom surface by etching.

16. The method of manufacturing a semiconductor device according to claim 14, wherein

the surface of the semiconductor layer is an Si plane, and

the step of covering the side surfaces with the mask is a step of forming a silicon oxide film on the bottom surface and the side surfaces by oxidizing the bottom surface and the side surfaces.

17. The method of manufacturing a semiconductor device according to claim 14, wherein

the step of forming the implantation layer is carried out before the step of forming the body region and the source region.

18. The method of manufacturing a semiconductor device according to claim 14, wherein

the step of forming the implantation layer is carried out after the step of forming the body region and the source region.